Abstract
There has been a significant rise in internet and wireless device users, raising the need for security to protect consumer data shared over open networks. Field Programmable Gate Arrays (FPGAs) are particularly desirable alternative for hardware implementation of cryptographic algorithm. This paper discusses hardware implementation of AES algorithm on a Field Programmable Gate Array (FPGA) platform with focus on high throughput and low area constraint. In the proposed design, an efficient pipelined architecture for AES encryption/decryption is realized using unrolled and external pipelining techniques. The proposed design is implemented on different families Virtex-5 and Spartan-6 of FPGA platform. This design obtained maximum throughput of 37.57 Gbps and 32.44 Gbps on Virtex-5 and Spartan-6, respectively. Along with throughput, it also got maximum frequency and high throughput per slice with significant number of slices.
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Acknowledgment
This work has been carried out under Information Security Education Awareness (ISEA) project phase – II & SMDP-C2SD project funded by Ministry of Electronics and Information Technology (MeitY), Govt. of India in the Department of Electronics and Communication Engineering at National Institute of Technology Raipur, India. Authors are thankful to the Ministry for the facilities provided under this project.
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Modi, P., Singh, P., Acharya, B., Verma, S. (2021). High Throughput Pipelined Architecture for AES Cipher. In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore. https://doi.org/10.1007/978-981-16-0275-7_29
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DOI: https://doi.org/10.1007/978-981-16-0275-7_29
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