Abstract
A novice scalable MBIT unit with MISR signature analysis is proposed in this project. Enhancement of MBIST architecture with signature analysis significantly improvises resolution of fault detection in memories in comparison to conventional MBIST Architecture. The proposed MBIST Algorithm is optimized by using only 14 states for 7 March algorithms, hence improvising the scalability of the MBIST without area overhead. The proposed architecture has an interface check MISR which features isolated detection of fault in memory interface and memory, hence improving resolution and accuracy. Rapid Fault check is enabled by Memory pre-check using MISR. Benchmarking for this project in terms on the accuracy, feature enhancement, scalability and the ability to detect early faults in less time are done via Random constrained verification of the developed RTL Model....
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Sasikumar, M., Bhakthavatchalu, R., Sreehari, K.N., Kumar, A.S. (2021). Scalable and Rapid Fault Detection of Memories Using MBIST and Signature Analysis. In: Merchant, S.N., Warhade, K., Adhikari, D. (eds) Advances in Signal and Data Processing . Lecture Notes in Electrical Engineering, vol 703. Springer, Singapore. https://doi.org/10.1007/978-981-15-8391-9_26
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