Abstract
The delta-sigma modulator is used as an oversampling ADC, which processes the signal input and the quantization noise by two distinct transfer functions, thus, separating the signal and noise into two distinct frequency bands. The resulting output of the modulator is digitally processed to separate the signal from noise. The performance of the ADC can be improved by increasing the order of the modulator, which imposes constraints on the system stability and on the input signal range. This paper examines the issues related to the design of a stable fourth-order MultistAge noise SHaping architecture(MASH) ADC, using two second-order delta-sigma modulators in cascade. The architecture achieves second-order Signal Transfer Function (STF) with fourth-order noise shaping . The modulator employs 32 MHz—clock, to obtain 8-bit sample sequence at 128 kHz sample rate. The resulting output is processed by a digital low pass filter to separate the signal from noise. The FIR filter is implemented using frequency sampling technique.
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Kotabagi, S.S., Subbanna Bhat, P. (2021). Design and Simulation of Fourth-Order Delta-Sigma Modulator-MASH Architecture. In: Nath, V., Mandal, J. (eds) Nanoelectronics, Circuits and Communication Systems. Lecture Notes in Electrical Engineering, vol 692. Springer, Singapore. https://doi.org/10.1007/978-981-15-7486-3_54
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DOI: https://doi.org/10.1007/978-981-15-7486-3_54
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