Abstract
Low-power two-stage OP-AMP is presented here. The OP-AMP receives 0.9 V supply voltage with variation of 0.8–1 V. Designed OP-AMP was simulated in 16 nm CMOS technology (PTM—Predictive technology models) with variation in supply voltage and temperature. The overall gain of two-stage OP-AMP was found to be greater than 40 dB for 0–80 °C temperature range. The nominal and worst-case power dissipation achieved are 873 nW and 3.3 µW, respectively.
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Agarwal, G., Dwivedi, V. (2021). Low-Power Two-Stage OP-AMP in 16 nm. In: Senjyu, T., Mahalle, P.N., Perumal, T., Joshi, A. (eds) Information and Communication Technology for Intelligent Systems. ICTIS 2020. Smart Innovation, Systems and Technologies, vol 195. Springer, Singapore. https://doi.org/10.1007/978-981-15-7078-0_62
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DOI: https://doi.org/10.1007/978-981-15-7078-0_62
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