Design and Analysis of an Improvised Fully Differential Amplifier

Abstract

This work proposes the design of an amplifier intended for low power applications, operating at an ultra-low voltage and exhibiting a low input-referred noise. The suggested structure implements a flip voltage follower (FVF) implemented in its biasing circuit and thereby demonstrates improvised design parameters as compared to the conventional single-stage fully differential amplifier (FDA). The design is an attempt to enhance the transconductance, slew rate and gain-bandwidth product (GBW). All the devices are operating in a weak inversion region such that the entire design is appropriate for low power applications. The circuit simulations have been performed in 180 nm CMOS SCL Cadence environment and are working at 0.6 V supply voltage. The simulation results report an increased gain by 7.81 dB and an enhanced phase margin by 3.85°. The design consumes a power of 1.07 μW with a total input-referred noise of 6.56 μV/$\surd$Hz @1 Hz. The gain-bandwidth product and slew rate are measured to be 485.28 kHz and 26.85 V/ms.