Skip to main content
SpringerLink
Log in

Architecture Description Languages

  • Living reference work entry
  • First Online:
Handbook of Computer Architecture

  • 226 Accesses

Abstract

Designing a processor is an arduous task. It involves not only defining the instruction-set architecture but also the various processor development tools such as compiler, instruction-set simulator, debugger, assembler, and linker. Moreover, an efficient hardware implementation of the entire microarchitecture is needed apart from verifying the entire design at every step while meeting various end user constraints. These tasks were traditionally done by various specialized teams, originating from an informal processor specification, which posed a significant challenge of maintaining design performance and consistency. The emergence of Architecture Description Languages (ADLs) addressed this challenge. In this chapter, the background of processor design automation flows and how ADLs fit into this narrative are discussed. Prominent ADLs, including commercial ones, are summarized to provide an idea about the inner workings of ADL-driven design flows.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

References

  • Amor HB, Bernier C, Prikryl Z (2021) A RISC-V ISA extension for ultra-low power IoT wireless signal processing. In: IEEE transactions on computers. Institute of Electrical and Electronics Engineers, pp 1–1. https://doi.org/10.1109/TC.2021.3063027.cea-03158876

    Chapter  Google Scholar 

  • Andes Custom Extension. http://www.andestech.com/en/productssolutions/andes-custom-extension/

  • Atasu K, Luk W, Mencer O, Ozturan C, Dundar G (2012) FISH: fast instruction synthesis for custom processors. IEEE Trans Very Large Scale Integr Syst 20(1):52–65

    Google Scholar 

  • Augustine S, Gauthier M, Leibson S, Macliesh P, Martin G, Maydan D, Nedeljkovic N, Wilson B (2009) Chapter 7 Generation and use of an ASIP software tool chain. In: Wolfgang E, Wolfgang M, Rainer D (eds) Hardware-dependent software: principles and practice. Springer, Berlin/Heidelberg, Germany

    Google Scholar 

  • Bailey B, Martin G (2010) ESL models and their application. Springer

    Book  Google Scholar 

  • Biswas P, Dutt ND, Pozzi L, Ienne P (2007) Introduction of architecturally visible storage in instruction set extensions. Comp Aided Design Integrated Circuits Syst IEEE Trans 26(3):435–446

    Article  Google Scholar 

  • Bit A (2020) 64-bit custom Math ISA in configurable 32-Bit RISC processor. In ICDSMLA 2019. Springer, Singapore, pp 564–575

    Google Scholar 

  • Bo W, Willems M (2015) Rapid architectural exploration in designing application-specific processors. White Paper, Synopsys. https://www.synopsys.com/dw/doc.php/wp/architectural_exploration_designing_application_specific_processors.pdf

  • Brown J, Epalza M. Automatically identifying and creating automatically identifying and creating accelerators directly from C code. Xilinx Xcelljournal, Issue 58, Third Quarter 2006. https://www.epfl.ch/labs/lap/wp-content/uploads/2018/05/BrownJul06_AutomaticallyIdentifyingAndCreatingAcceleratorsDirectlyFromCCode_Xcell.pdf

  • Cadence Tensilica Processor IP. https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html

  • Castrillon J, Zhang D, Kempf T, Vanthournout B, Leupers R, Ascheid G (2009) Task management in MPSoCs: an ASIP approach. In: Proceedings of the 2009 international conference on computer-aided design (ICCAD '09). Association for Computing Machinery, New York, pp 587–594. https://doi.org/10.1145/1687399.1687508

    Chapter  Google Scholar 

  • Chattopadhyay A, Kammler D, Witte EM, Schliebusch O, Ishebabi H, Geukes B, Leupers R, Ascheid G, and Meyr H (2006a) Automatic low power optimizations during ADL-driven ASIP design. In VLSI design, automation and test, 2006 international symposium on, pp 1–4,

    Google Scholar 

  • Chattopadhyay A, Geukes B, Kammler D, Witte EM, Schliebusch O, Ishebabi H, Leupers R, Ascheid G, Meyr H (2006b) Automatic ADL-based operand isolation for embedded processors. In Proceedings of the conference on design, automation and test in Europe: Proceedings, DATE ‘06, pp 600–605

    Google Scholar 

  • Chattopadhyay A, Sinha A, Zhang D, Leupers R, Ascheid G, Meyr H (2006c) Integrated verification approach during ADL-driven processor design. In Rapid system prototyping, 2006. Seventeenth IEEE international workshop on, pp 110–118

    Google Scholar 

  • Chattopadhyay A, Chen X, Ishebabi H, Leupers R, Ascheid G, Meyr H (2008) High-level modelling and exploration of coarse grained re-configurable architectures. In Proceedings of the conference on design, automation and test in Europe, DATE ‘08, pp 1334–1339

    Google Scholar 

  • Chattopadhyay A, Leupers R, Meyr H, Ascheid G (2009) Language-driven exploration and implementation of partially re-configurable ASIPs. Springer

    Google Scholar 

  • Chen X, Minwegen A, Hussain SB, Chattopadhyay A, Ascheid G, Leupers R (2015) Flexible, efficient multimode mimo detection by using reconfigurable asip. IEEE Trans Very Large Scale Integrat (VLSI) Syst 23(10):2173–2186

    Article  Google Scholar 

  • Chisel Programming Language. https://www.chisel-lang.org

  • Cmelik B, Keppel D (1994) Shade: a fast instruction-set simulator for execution profiling. In Proceedings of the 1994 ACM SIGMETRICS conference on measurement and modeling of computer systems, SIGMETRICS ‘94, pp 128–137

    Google Scholar 

  • Codasip. https://codasip.com

  • Cox S, Taussig D (2016) Extending RISC-V for application-specific requirements. 5th RISC-V Workshop, November 29, 2016

    Google Scholar 

  • Dang TN, Roychoudhury A, Mitra T, Mishra P (2009) Generating test programs to cover pipeline interactions. In Proceedings of the 46th annual design automation conference, DAC ‘09, pp 142–147

    Google Scholar 

  • Efland G et al (2016) High performance DSP for vision, imaging and neural networks. Hot Chips, Cupertino

    Google Scholar 

  • Fauth A, Knoll A (1993) Automated generation of DSP program development tools using a machine description formalism. In Acoustics, speech, and signal processing, 1993 IEEE international conference on, vol 1, pp 457–460

    Google Scholar 

  • Freericks M (1993) The nML machine description formalism. TU Berlin CS Dept. Technical Report TR SM-IMP/DIST/08

    Google Scholar 

  • Geuzebroek J (2014) Leveraging processor extensibility to build an ultra low-power embedded subsystem. Synopsys white paper

    Google Scholar 

  • Goodwin D, Pekov D (2003) Automatic generation of application specific processors. Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems (CASES-2003), pp 137–147

    Google Scholar 

  • Goossens G, Lanneer D, Geurts W, Van Praet J (2006) Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. Int Symp System-on-Chip. https://doi.org/10.1109/ISSOC.2006.321968

  • Gries M, Keutzer K (2005) Building ASIPs: the mescal methodology. Springer, Berlin/Heidelberg, Germany

    Google Scholar 

  • V. Grimblatt, G. Ferré, F. Rivet, C. Jego and N. Vergara, "Precision agriculture for small to medium size farmers – an IoT approach," 2019 IEEE Int Symp Circuits Syst (ISCAS), 2019, pp. 1–5, https://doi.org/10.1109/ISCAS.2019.8702563

  • Gupta A, Pal A (2015) Accelerating SVM on ultra low power ASIP for high throughput streaming applications. In: 2015 28th international conference on VLSI design. IEEE

    Google Scholar 

  • Hadjiyiannis G, Hanono S, Devadas S (1997) ISDL: an instruction set description language for retargetability. In Proceedings of the 34th annual design automation conference, DAC ‘97, pp 299–302

    Google Scholar 

  • Halambi A, Grun P, Ganesh V, Khare A, Dutt N, Nicolau A. EXPRESSION: a language for architecture exploration through compiler/simulator retargetability. In Design, automation and test in Europe conference and exhibition 1999. Proceedings, pp 485–490, March 1999

    Google Scholar 

  • Hartoog MR, Rowson JA, Reddy PD, Desai S, Dunlop DD, Harcourt EA, Khullar N (1997) Generation of software tools from processor descriptions for hardware/software codesign. In Proceedings of the 34th annual design automation conference, DAC ‘97, pp 303–306

    Google Scholar 

  • Hassan MA, Imai M ASIP Meister: an ASIP design environment. DATE 2005 University Booth, https://www.edacentrum.de/system/files/files/veranstaltungen/2005/date05/ubooth/descriptions/Description_sw_ASIP.pdf

  • Hohenauer M, Scharwaechter H, Karuri K, Wahlen O, Kogel T, Leupers R, Ascheid G, Meyr H, Braun G, van Someren H (2004) A methodology and tool suite for C compiler generation from ADL processor models. In Proceedings of the conference on design, automation and test in Europe – Volume 2, DATE ‘04, 2004

    Google Scholar 

  • Hohenauer M, Schumacher C, Leupers R, Ascheid G, Meyr H, Someren Hv (2006) Retargetable code optimization with SIMD instructions. In CODES+ISSS ‘06: Proceedings of the 4th international conference on hardware/software codesign and system synthesis. ACM, New York, pp 148–153

    Google Scholar 

  • Hohenauer M, Engel F, Leupers R, Ascheid G, Meyr H, Bette G, Singh B (2008) Retargetable code optimization for predicated execution. In Proceedings of the conference on design, automation and test in Europe, DATE ‘08, pp 1492–1497

    Google Scholar 

  • Husár A, Trmac M, Hranac J, Hruska T, Masarík K (2010) Automatic C compiler generation from architecture description language ISAC. MEMICS:47–53

    Google Scholar 

  • Inoue A, Tomiyama H, Fajar E, Yasuura NH, Kanbara H (1998) A programming language for processor based embedded systems. In Proc. of APCHDL, pp 89–94

    Google Scholar 

  • Itoh M, Higaki S, Sato J, Shiomi A, Takeuchi Y, Kitajima A, Imai M (2000a) PEAS-III: an ASIP design environment. In Computer design, 2000. Proceedings. 2000 international conference on, pp 430–436

    Google Scholar 

  • Itoh M, Takeuchi Y, Imai M, Shiomi A. Synthesizable HDL generation for pipelined processors from a micro-operation description. IEICE Trans. Fundamentals, March 2000b

    Google Scholar 

  • Jamma D et al (2016) Design exploration of ASIP architectures for the K-nearest neighbor machine-learning algorithm. In: 2016 28th international conference on microelectronics (ICM). IEEE

    Google Scholar 

  • Jani D, Benson C, Dixit A, Martin G (2005) Chapter 18 Functional verification of configurable embedded processors. In: Bailey B (ed) The functional verification of electronic systems: an overview from various points of view. IEC Press, Chicago, US

    Google Scholar 

  • Kalluri SS. Securing offload engines for A robust secure SoC system. https://semiengineering.com/securing-offload-engines-for-a-robust-secure-soc-system/

  • Kammler D, Zhang D, Schwabe P, Scharwaechter H, Langenberg M, Auras D, Ascheid G, Mathar R (2009) Designing an asip for cryptographic pairings over barreto-naehrig curves. In: Clavier C, Gaj K (eds) Cryptographic hardware and embedded systems – CHES 2009. Springer, Berlin, Heidelberg, pp 254–271

    Chapter  MATH  Google Scholar 

  • Karuri K, Chattopadhyay A, Hohenauer M, Leupers R, Ascheid G, Meyr H (2007) Increasing data-bandwidth to instruction-set extensions through register clustering. In IEEE/ACM international conference on computer-aided design (ICCAD)

    Google Scholar 

  • Karuri K, Chattopadhyay A, Chen X, Kammler D, Hao L, Leupers R, Meyr H, Ascheid G (2008) A design flow for architecture exploration and implementation of partially reconfigurable processors. IEEE Trans Very Large Scale Integr Syst 16(10):1281–1294

    Article  Google Scholar 

  • Khare A, Savoiu N, Halambi A, Grun P, Dutt N, Nicolau A (1999) V-SAT: a visual specification and analysis tool for system-on-chip exploration. In EUROMICRO conference, 1999. Proceedings. 25th, vol 1, pp 196–203

    Google Scholar 

  • Kraemer S, Gao L, Weinstock J, Leupers R, Ascheid G, Meyr H (2007) HySim: a fast simulation framework for embedded software development. In: CODES+ISSS ‘07: proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis, pp 75–80

    Chapter  Google Scholar 

  • Lanneer D, Praet J, Kifli A, Schoofs K, Geurts W, Thoen F, Goossens G (1995) CHESS: retargetable code generation for embedded DSP processors. Code Generation for Embedded Processors, pp 85–102

    Google Scholar 

  • Leupers R, Marwedel P (1998) Retargetable code generation based on structural processor description. Des Autom Embed Syst 3(1):75–108

    Article  Google Scholar 

  • Leupers R, Karuri K, Kraemer S, Pandey M (2006) A design flow for configurable embedded processors based on optimized instruction set extension synthesis. In: DATE ‘06: proceedings of the conference on design, automation and test in Europe. European Design and Automation Association, pp 581–586

    Google Scholar 

  • Leupers R Chattopadhyay A, Dutt N, Mishra P (2016) Processor modeling and design tools. Chapter 9 of EDA for IC system design, verification and testing (Volume 1 of the Electronic Design Automation for Integrated Circuits Handbook, Second Edition), edited by L. Lavagno, I. Markov, G. Martin, and L. Scheffer, CRC Press/Taylor and Francis

    Google Scholar 

  • Machetti S (2018) ASIP design for motion estimation in video compression algorithms. PhD Thesis. Politecnico di Torino

    Google Scholar 

  • Makimoto T (2002) The hot decade of field programmable technologies. IEEE international conference on field-programmable technology, 2002. (FPT). Proceedings, pp 3–6. https://doi.org/10.1109/FPT.2002.1188657

  • Martin G, Nicolaescu D (2018) Enhancing DSP design productivity with automated generators. unpublished paper, 2018. (Available by emailing gmartin@ieee.org)

  • Marwedel P (1979) The MIMOLA design system: detailed description of the software system. 16th Design Automation Conference, pp 59–63. https://doi.org/10.1109/DAC.1979.1600089

  • Maydan D (2011) Evolving voice and audio requirements for smartphones. Linley Technology Mobile Conference

    Google Scholar 

  • Meyr H, Chattopadhyay A, Leupers R (2008) LISA: a uniform ADL for embedded processor modelling, implementation and software toolsuite generation. In: Processor description languages, edited by P. Mishra and N. Dutt, pp 95–130

    Google Scholar 

  • Mishra P (2005) Processor validation: a top-down approach. Potentials, IEEE 24(1):29–33

    Article  Google Scholar 

  • Mishra P, Dutt N (2004a) Modeling and validation of pipeline specifications. ACM Trans Embed Comput Syst 3(1):114–139

    Article  Google Scholar 

  • Mishra P, Dutt N (2004b) Graph-based functional test program generation for pipelined processors. In Design, automation and test in Europe conference and exhibition, 2004. Proceedings, vol 1, pp 182–187

    Google Scholar 

  • Mishra P, Dutt N (2005a) Functional coverage driven test generation for validation of pipelined processors. In Proceedings of the conference on design, automation and test in Europe - Volume 2, DATE ‘05, pp 678–683

    Google Scholar 

  • Mishra P, Dutt N (2005b) Architecture description languages for programmable embedded systems. In: IEE Proceedings on computers and digital techniques

    Google Scholar 

  • Mishra P, Dutt N (eds) (2008) Processor description languages. Morgan Kaufmann Publishers Inc

    Google Scholar 

  • Mishra P, Dutt N, Tomiyama H (2003) Towards automatic validation of dynamic behavior in pipelined processor specifications. Des Autom Embed Syst 8(2–3):249–265

    Article  Google Scholar 

  • Mishra P, Kejariwal A, Dutt N (2004) Synthesis-driven exploration of pipelined embedded processors. In VLSI design, 2004. Proceedings of the 17th international conference on, pp 921–926

    Google Scholar 

  • Nohl A, Braun G, Schliebusch O, Leupers R, Meyr H, Hoffmann A (2002) A universal technique for fast and flexible instruction-set architecture simulation. In Proceedings of the 39th annual design automation conference, DAC ‘02, pp 22–27

    Google Scholar 

  • Nohl A, Greive V, Braun G, Hoffman A, Leupers R, Schliebusch O, Meyr H. (2003) Instruction encoding synthesis for architecture exploration using hierarchical processor models. In Design automation conference, 2003. proceedings, pp 262–267

    Google Scholar 

  • Ogawa HS, Luther TE, Ricardini JE, Cunha H, Simplicio M Jr, Aranha DF, Derwig R, Kupwade-Patil H (2019) Accelerated v2x provisioning with extensible processor platform. Cryptology ePrint Archive, Report 2019/1039, x. https://ia.cr/2019/1039

  • Pees S, Hoffmann A, Meyr H (2000) Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans Des Autom Electron Syst 5(4):815–834

    Article  Google Scholar 

  • Podivinsky J, Cekan O, Krcma M, Burget R, Hruska T, Kotasek Z (2018) A processor optimization framework for a selected application. IEEE East-West design & test symposium (EWDTS), pp 1–11. https://doi.org/10.1109/EWDTS.2018.8524733

  • Pothineni N, Kumar A, Paul K. (2008) Exhaustive enumeration of legal custom instructions for extensible processors. In VLSI design, 2008. VLSID 2008. 21st international conference on, pp 261–266

    Google Scholar 

  • Press Release. Codasip appoints Ron Black as CEO. 2 December 2021. https://codasip.com/2021/12/02/codasip-appoints-ron-black-as-ceo/

  • PÅ™ikryl Z (2019) Code density improvements beyond the C standard extension. RISC-V Summit

    Google Scholar 

  • PÅ™ikryl Z. Creating domain-specific processors using custom RISC-V ISA instructions. Codasip White Paper, September 23, 2020. https://codasip.com/2020/09/23/creating-domain-specific-processors-using-custom-risc-v-isa-instructions/

  • Qin W, Malik S (2002) Architecture description languages for retargetable compilation. In: Compiler design handbook: optimizations & machine code generation. CRC Press, Chicago, US, pp 535–564

    Google Scholar 

  • Rajesh V, Moona R. Processor modeling for hardware software codesign. In VLSI design, 1999. Proceedings. twelfth international conference on, pp 132–137, Jan 1999

    Google Scholar 

  • Rakossy ZE, Naphade T, Chattopadhyay A (2012) Design and analysis of layered coarse-grained reconfigurable architecture. In Reconfigurable computing and FPGAs (ReConFig), 2012 international conference on, pp 1–6

    Google Scholar 

  • Rakossy ZE, Aponte AA, Chattopadhyay A (2013) Exploiting architecture description language for diverse ip synthesis in heterogeneous mpsoc. In Reconfigurable computing and FPGAs (ReConFig), 2013 international conference on, pp 1–6

    Google Scholar 

  • RAO, Jinli et al (2018) Design exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V processor. IEICE Trans Inf Syst 101(11):2698–2705

    Article  Google Scholar 

  • Reshadi M, Mishra P, Dutt N (2003) Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. In Proceedings of the 40th annual design automation conference, DAC ‘03, pp 758–763

    Google Scholar 

  • RISC-V Custom Instructions – Design, Development And Deployment, February 24, 2021. http://www.andestech.com/en/2021/02/24/risc-v-custom-instructions-design-development-and-deployment-%E2%94%82-2021-webinar/

  • Roeven H, Coninx J, Ade M (2004) CoolFlux DSP-The embedded ultra low power C-programmable DSP core. Proceedings of the International Signal Proceedings of Conference (GSPx)

    Google Scholar 

  • Rounioja K, Puusaari K (2006) Implementation of an hsdpa receiver with a customized vector processor. In: 2006 international symposium on system-on-chip. IEEE

    Google Scholar 

  • Rowen C (2012) Power/performance breakthrough for LTE advanced handsets. Linley Mobile Conference, April 16, 2012

    Google Scholar 

  • Sanghavi H, Andrews N (2008) TIE: an ADL for designing application-specific instruction-set extensions. Processor description languages, edited by P. Mishra and N. Dutt, pp 183–216

    Google Scholar 

  • Saponara S, Fanucci L, Marsi S, Ramponi G, Kammler D, Witte EM (2007) Application-specific instruction-set processor for retinex-like image and video processing. IEEE Trans Circuits Syst II Express Briefs 54(7):596–600

    Article  Google Scholar 

  • Schliebusch O, Chattopadhyay A, Leupers R, Ascheid G, Meyr H, Steinert M, Braun G, Nohl A (2004a) RTL processor synthesis for architecture exploration and implementation. In: Design, automation and test in Europe conference and exhibition, 2004. Proceedings, vol 3, pp 156–160

    Chapter  Google Scholar 

  • Schliebusch O, Kammler D, Chattopadhyay A, Leupers R, Ascheid G, Meyr H (2004b) Automatic generation of JTAG interface and debug mechanism for ASIPs. In GSPx, 2004. Proceedings

    Google Scholar 

  • Selim Z, et al An efficient ASIP design methodology. https://www.design-reuse.com/articles/24082/asip-design-methodology.html

  • Siska C (1998) A processor description language supporting retargetable multi-pipeline dsp program development tools. In Proceedings of the 11th international symposium on system synthesis, ISSS ‘98, pp 31–36

    Google Scholar 

  • Synopsys ASIP Designer. https://www.synopsys.com/designware-ip/processor-solutions/asips-tools.html, https://www.synopsys.com/dw/ipdir.php?ds=asip-designer

  • Synopsys ASIP Designer. https://www.synopsys.com/designware-ip/processor-solutions/asips-tools.html, and https://www.synopsys.com/dw/ipdir.php?ds=asip-designer

  • Synopsys DesignWare ARC Processor Cores. https://www.synopsys.com/designwareip/processor-solutions.html

  • The MDES User Manual. http://www.trimaran.org

  • Tomiyama H, Halambi A, Grun P, Dutt N, Nicolau A (1999) Architecture description languages for systems-on-chip design. In: In the sixth Asia Pacific conference on chip design language, pp 109–116

    Google Scholar 

  • Trmac M, Husár A, Hranac J, Hruska T, Masarík K (2010) Instructor selector generation from architecture description. MEMICS:109–115

    Google Scholar 

  • van der Wolf P, Derwig R (2013) Modular SoC integration with subsystems The audio subsystem case. Design, automation & test in Europe conference & exhibition (DATE), 2013, pp 157–162. https://doi.org/10.7873/DATE.2013.045

  • Wahlen O, Hohenauer M, Leupers R, Meyr H (2003) Instruction scheduler generation for retargetable compilation. Design Test Comp 20(1):34–41. IEEE

    Article  Google Scholar 

  • Wang Z, Chattopadhyay A (2017) High-level estimation and exploration of reliability for multi-processor system-on-chip. In Springer

    Google Scholar 

  • Wang S, Malik S. (2003) Synthesizing operating system-based device drivers in embedded systems. In Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, CODES+ISSS ‘03, pp 37–44

    Google Scholar 

  • Wang Z et al (2012) ASIC synthesis using architecture description language. Proceedings of technical program of 2012 VLSI design, automation and test. IEEE

    Google Scholar 

  • Watson RNM, Moore SW, Sewell P, Neumann PG (2019) An Introduction to CHERI. Technical Report, UCAM-CL-TR-941, University of Cambridge

    Google Scholar 

  • Witchel E, Rosenblum M (1996) Embra: fast and flexible machine simulation. In: Proceedings of the 1996 ACM SIGMETRICS international conference on measurement and modeling of computer systems, SIGMETRICS ‘96, pp 68–79

    Chapter  Google Scholar 

  • Xie H Wang Z, Wang L, Chattopadhyay A (2013) Power modeling and estimation during adl-driven embedded processor design. In Energy aware computing systems and applications (ICEAC), 2013 4th annual international conference on, pp 97–102

    Google Scholar 

  • Zhang D, et al (2013) Optimized communication architecture of MPSoCs with a hardware scheduler: a system-level analysis. Adoption and optimization of embedded and real-time communication systems. IGI Global, pp 163–180

    Google Scholar 

  • Zhu J, Gajski DD (1999) A retargetable, ultra-fast instruction set simulator. In Proceedings of the conference on design, automation and test in Europe, DATE ‘99

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

  2. Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China

    Zheng Wang

  3. Independent Consultant, Pleasanton, CA, USA

    Grant Martin

Authors
  1. Anupam Chattopadhyay
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Zheng Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Grant Martin
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Zheng Wang .

Editor information

Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

Section Editor information

  1. Center for Advancing Electronics Dresden, TU Dresden, Dresden, Germany

    Jeronimo Castrillon

  2. Pleasanton, CA, USA

    Grant Martin M.Math

Rights and permissions

Reprints and permissions

Copyright information

© 2022 Springer Nature Singapore Pte Ltd.

About this entry

Check for updates. Verify currency and authenticity via CrossMark

Cite this entry

Chattopadhyay, A., Wang, Z., Martin, G. (2022). Architecture Description Languages. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_18-1

Download citation

  • DOI: https://doi.org/10.1007/978-981-15-6401-7_18-1

  • Received:

  • Accepted:

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-6401-7

  • Online ISBN: 978-981-15-6401-7

  • eBook Packages: Springer Reference EngineeringReference Module Computer Science and Engineering

Publish with us

Policies and ethics

Search

Navigation