Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity

Abstract

The digital verification with Universal Verification Methodology (UVM) provides vast opportunities for automation. The momentous themes in the context of digital verification are constraint random stimulus generation, functional coverage, and self-checking test benches that make digital verification very robust. However, analog verification is still a manual process. Therefore, the demand is to transform analog verification techniques into an automated process in the context of digital-centric Mixed-Signal verification for more coverage. A new verification approach that simulates Mixed-Signal Design Under Test (DUT), which contains Register Transfer Logic (RTL), SPICE netlist, and Verilog-AMS models or Real Number Model (RNM) blocks has been demonstrated in the paper that describes the Mixed-Signal simulation environment and simulation techniques to achieve more simplistic yet very powerful strategies to address Mixed-Signal verification challenges.

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