Abstract
This paper presents design exploration of a logic-based high-performance content-addressable memory (LH-CAM), which is the first time a CAM is implemented using the logical resources on field-programmable gate array (FPGA). Different sizes of LH-CAM are implemented on Xilinx Virtex-6 FPGA device. Speed, logical resources, and power consumption of all the sizes are presented. It is concluded that the resource utilization of LH-CAM increases with increase in size. A verdict on the efficiency and relationship of size, speed, and power consumption of LH-CAM is given. Besides exploration, an updating mechanism is added in LH-CAM architecture, which makes run-time update of the CAM possible.
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Mujahid, O., Ullah, Z., Hafeez, A., Fouzder, T. (2020). Design Exploration of LH-CAM with Updating Mechanism. In: Uddin, M.S., Bansal, J.C. (eds) Proceedings of International Joint Conference on Computational Intelligence. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-3607-6_38
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DOI: https://doi.org/10.1007/978-981-15-3607-6_38
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