Abstract
The usage of a CVNS neuron of blended flag of low power and configuration is introduced. The straight guess by parts in the simple area is utilized for the actuation work. The usage of the simple neural system has a constrained accuracy, so this neuron is proposed. Less simple digits of the nonstop esteem numerical framework (CVNS) are supplanted by general advanced yields of a sigmoid neuron, while in the meantime the most extreme methodology blunder continues as before as computerized structures. The execution of ASIC and the learning of chips for fitting neuronal chips is the aftereffect of this proposed CVNS neuron. Utilizing circuits of current mode, the VLSI usage of the neuron will be completed. The consequences of the usage contrast positively and the structures recently created regarding zone, postponement and vitality utilization.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Zamanlooy B, Mirhassani M (2017) An analog CVNS-based sigmoid neuron for precise neurochips. IEEE Trans Very Large Scale Integr (VLSI) Syst 25:894–906
Tsai C-H, Chih Y-T, Wong WH, Lee C-Y (2015) A hardware efficient sigmoid function with adjustable precision for a neural network system. IEEE Trans Circuits Syst II Express Briefs 62(11):1073–1077. https://doi.org/10.1109/tcsii.2015.2456531
Zamanlooy B, Mirhassani M (2015) CVNS synapse multiplier for robust neurochips with on-chip learning. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(11):2540–2551
Khodabandehloo G, Mirhassani M, Ahmadi M (2011) CVNS-based storage and refreshing scheme for a multi-valued dynamic memory. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(8):1517–1521
Khodabandehloo G, Mirhassani M, Ahmadi M (2012) A prototype CVNS distributed neural network using synapse-neuron modules. IEEE Trans Circuits Syst I Reg Papers 59(7):1482–1490
Amin H, Curtis K, Hayes-Gill B (1997) Piecewise linear approximation applied to nonlinear function of a neural network. IEE Proc Circuits Devices Syst 144(6):313–317
Prasad GRK (2018) Design and verification of AXI APB bridge using system verilog. JARDCS 10(6):1401–1408
Sankar Rao DG (2018) Analysis of static and dynamic CMOS low power high speed NP domino logic. Int J Adv Trends Comput Sci Eng 7(6):99–102
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this chapter
Cite this chapter
Shameem, S. et al. (2020). Low Power Mixed Signal with CVNS Based Neuron Chip. In: Gunjan, V., Senatore, S., Kumar, A., Gao, XZ., Merugu, S. (eds) Advances in Cybernetics, Cognition, and Machine Learning for Communication Technologies. Lecture Notes in Electrical Engineering, vol 643. Springer, Singapore. https://doi.org/10.1007/978-981-15-3125-5_42
Download citation
DOI: https://doi.org/10.1007/978-981-15-3125-5_42
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-3124-8
Online ISBN: 978-981-15-3125-5
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)