Design, Development and Validation of Fault-Tolerant Processor and Integrated Development Environment for Space and Defence Applications: Indigenous Initiative

Abstract

Space and defence electronics system demands higher reliability for its operation in harsh (Maurer et al. in John Hopkins APL Tech Dig 28, 2008 [1]) and tough application environments. Development of processor (Azambuja et al. in IEEE Trans Nucl Sci 59, 2012 [2]) based electronics systems has advantages over sequencer logics, viz. high operating frequency, handle complex algorithm for autonomous operations, supports multiinput and multioutput systems, low form factor, ultra-low-power consumption and increased reliability. The operation of processor under various environmental conditions and its uninterrupted operations pave way to achieve successful missions. Most of the on-board computers for the space and defence systems are subjected to harsh environments due to cosmic radiations(aerial), high temperature, vibrations, sand and dust. Modular redundancy concepts aid to improve reliability however at the cost of increased form factor and enhanced power requirements. Researchers across the globe evolved with various methods and techniques to increase the ruggedness of the electronics systems. Traditional design hardening techniques viz. modular redundancies, parity algorithms, cyclic redundancy checks, single error correction and double error detection are in use to develop the fault-tolerant on-board computers. Since most of the fault-tolerant processors developed using in-house design, process hardening techniques for specific purpose, the availability of the same for the strategic programs and critical applications is limited and export controlled. To mitigate the scenarios, an indigenous effort has been made to architect, design, develop and validate the fault-tolerant processor using DRDO processor core (Series-A). The core is indigenously developed by DRDO. Using the fault-tolerant design methods, the indigenous processor core is upgraded to a fault-tolerant core. The core is RISC-based 32-bit architecture. The non-fault tolerant (FT) core is architected to incorporate the FT feature using the in-house and traditional techniques, viz. modular redundancy, single error correction and double error detection for FFs and registers, parity logics for memories. To provide the operational compatibility and to estimate the performance of FT-core using the user’s application algorithm, an integrated development environment (IDE) is designed, developed and validated. The FT-core with a frequency of up to 50 MHz in FPGA is validated using the application program for the function-A (aerial) and function-B (ground) strategic systems. The functional performance was on par with the industry architecture. The timing performance is satisfactory and met the user’s functional requirement. To meet the high performance and computational intensive requirements of the futuristic programs, the FT-core to be developed using dual or quad-core approach with appropriate fault-tolerant techniques.