Abstract
With the rapid increase of clocked/synchronous digital circuits, there is also an increase in the complexity of circuits. This complexity results in clock skew and synchronization problem in the nodes, which are on the critical path of the circuit. This paper proposes a clock system architecture (CSA) with clock gaters to modify the clock as per system requirement to match the desired characteristics. The clock architecture is the heart of any embedded system. The proposed technique proposes a novel solution for modifying the clock using clock system architecture (CSA). This unique approach can configure digital systems in various low-power modes as per the clock frequencies. The proposed clock system architecture was designed and simulated for functional verification.
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Saxena, A., Shinghal, K., Misra, R., Agarwal, A. (2020). Clock System Architecture for Digital Circuits. In: Singh Tomar, G., Chaudhari, N.S., Barbosa, J.L.V., Aghwariya, M.K. (eds) International Conference on Intelligent Computing and Smart Communication 2019. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-0633-8_134
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DOI: https://doi.org/10.1007/978-981-15-0633-8_134
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