Abstract
A power-efficient and moderate resolution Successive Approximation Register (SAR) ADC design is implemented in this paper. ADC is an important electronic circuit in biomedical electronic systems. Low-power operation and compacted chip size are the essential requirements of various biomedical systems. Also to precisely detect the various natural signals originating from the human body, resolution is of utmost importance. Among the different ADC designs available, SAR-type ADC has shown superior capabilities in terms of low-power operation, better resolution, a small form factor, and less die area. This proposed paper comprises of capacitive type Digital-to-Analog Converter (DAC) based on charge distribution method, SAR logic implemented using basic logic gates, and low-power operated comparator circuit. The inner blocks of the proposed architecture were designed and simulated in CMOS 130 nm N-well technology operated with VDD of 1.2 V supply. The simulated Integral Nonlinearity error (INL) and Differential Nonlinearity error (DNL) are between 0.2/−0.03 LSB and 0.41/−0.22 LSB, respectively. The proposed ADC exhibits SNDR (signal-to-noise plus distortion ratio) of 42.3 dB and reside in a die area of 0.106 mm2.
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Al-Naamani, Y.M.A., Lokesh Krishna, K., Krishna Mohan, A. (2020). An 8-Bit Charge Redistribution SAR ADC. In: Kalam, A., Niazi, K., Soni, A., Siddiqui, S., Mundra, A. (eds) Intelligent Computing Techniques for Smart Energy Systems. Lecture Notes in Electrical Engineering, vol 607. Springer, Singapore. https://doi.org/10.1007/978-981-15-0214-9_63
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DOI: https://doi.org/10.1007/978-981-15-0214-9_63
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