Equivalence Checking Between System-Level Descriptions by Identifying Potential Cut-Points

Abstract

Symbolic simulation is one of the most important equivalence checking method, but it can not deal with large designs due to the limited capacity of BDD and SAT/SMT. Cut-points technique is used with symbolic simulation to verify the large size of designs. However, the existing approaches need the mapping information, which is not easily obtained in the verification process. This paper presents a new equivalence checking method against system-level descriptions without mapping information of variables. Our method first randomly simulate the designs under verification to generate potential cut-points set. If some output variables do not belong to the potential cut-points set, return not equivalent. Second, our method select and remove the potential cut-point pair from the set and slice the program according to it. Third, we symbolically simulate the slice and compare the results. If the corresponding potential cut-points are really equivalent, they are put into equivalent set. Finally, the process is repeated until the potential cut-points set is empty or some outputs are not equivalent. Our method can check the equivalence of designs without mapping information and decrease the verification size. The experimental results shows the effectiveness and efficiency of our proposed method.