Abstract
In this paper, a hardware-implemented architecture for the efficient sub-pixel interpolation in the HDTV encoder and decoder is proposed. As for the luma component, a balanced interpolator structure is adopted. The luma module consists of seven half-pixel interpolation components and a quarter-pixel interpolation component. This module can accelerate the operation in luma interpolation and reduce the possible glitches. In order to implement the eighth-pixel interpolation in the chroma component, we propose an interpolation architecture that only includes shifters and adders. The hardware proposed in this paper can compute the interpolation for different pixels with less gates and faster speed. The FPGA experiment shows that this structure can work at 65.58 MHz and can meet the requirement of video codec.
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Wu, M. (2020). Hardware Implementation of the Sub-pixel Interpolation in the HDTV Video Codec. In: Jain, V., Patnaik, S., Popențiu Vlădicescu, F., Sethi, I. (eds) Recent Trends in Intelligent Computing, Communication and Devices. Advances in Intelligent Systems and Computing, vol 1006. Springer, Singapore. https://doi.org/10.1007/978-981-13-9406-5_75
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DOI: https://doi.org/10.1007/978-981-13-9406-5_75
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