Abstract
Multipliers play an important role in any processor or computing machine. The performance of arithmetic circuits is evaluated from the performance of multipliers of those circuits. The conventional multiplier circuits process only two binary data at a time for multiplication. This paper proposes a methodology to multiply three binary numbers at once. This methodology reduces the complexity of the circuit for multiplying three binary numbers as compared to the existing methods of multiplying. When implemented in a circuit, this has turned out to increase the performance of the multiplier based on proposed methodology in terms of power, gates and delay as compared to existing multipliers. Based on simulation results for design of circuit for multiplying three 4-bit binary numbers, the proposed methodology shows a reduction of 37.56, 62.90 and 41.35% in propagation delay, power consumption and gate counts, respectively, as compared to existing techniques.
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Mukherjee, A., Hore, N., Kumar, V. (2019). A Novel Methodology for Multiplication of Three n-Bit Binary Numbers. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 900. Springer, Singapore. https://doi.org/10.1007/978-981-13-3600-3_72
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DOI: https://doi.org/10.1007/978-981-13-3600-3_72
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