Abstract
This paper presents a novel 9T SRAM (static random-access memory) cell design with reduced leakage power and high performance. The design makes use of a sleep transistor so as to curtail the leakage power by eliminating the formation of a direct connection between the supply voltage (VDD) and ground. The results are compared with existing 9T SRAM cell with the same transistor sizing and parameter variations. The designed SRAM cell has decoupled read and write operations and is simulated using Cadence at 45 nm CMOS technology. At 0.8 V, the proposed cell has an improvement of 31.78% and 73.66% respectively in dynamic and static powers when compared with the reported 9T SRAM cell. Also, nearly 36% improvement in power delay product (PDP) is achieved with the proposed design.
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Singh, B., Kumar, M., Singh Ubhi, J. (2019). Comparative Analysis of Standard 9T SRAM with the Proposed Low-Power 9T SRAM. In: Rawat, B., Trivedi, A., Manhas, S., Karwal, V. (eds) Advances in Signal Processing and Communication . Lecture Notes in Electrical Engineering, vol 526. Springer, Singapore. https://doi.org/10.1007/978-981-13-2553-3_52
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DOI: https://doi.org/10.1007/978-981-13-2553-3_52
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