A Novel Design of Carry Select Adder (CSLA) for Low Power, Low Area, and High-Speed VLSI Applications

Abstract

Ripple carry adders (RCAs) suffer from large propagation delay due to carry out propagation from one stage to another. Various fast adders like carry select adder, carry look ahead adder, carry skip adder, and carry bypass adder have been proposed in literature. Among these adders, carry select adder has been regarded as the fastest in term of speed. Existing carry select adders suffer from high power consumption, layout area, and propagation delay. This paper presents a new design for carry select adder where the sum is generated and inverted for carry-in 0 and 1 respectively and the final selection of sum is made with the help of multiplexer. The proposed design is extended to build 4-bit, 8-bit, 16-bit and 32-bit carry select adder. The proposed design of 32-bit carry select adder shows an improvement up to 25.11%, 42.04%, and 24.70% in reduction of average power, propagation delay, and gate count respectively as compared to the best existing design of carry select adders available in literature. Simulation and synthesis of all the circuits have been carried out in Cadence Virtuoso Tool using 45 nm technology.