Abstract
As wireless communication equipment’s are demanding higher speed of operation, low power and into the digital domain, it becomes essential to design a high speed and low power ADC. This paper presents a novel power efficient, high-speed two step analog to digital converter (ADC) architecture combining two whole Flash ADCs with feed forward circuitry. The proposed circuit has been designed to overcome the drawbacks of the conventional flash ADC which draws more power due to the high speed comparator bank. Also the proposed two-step ADC employs a modified double tail comparator circuit which operates at high speed and consumes less power. The individual block of two step flash ADC is designed, simulated and implemented in CMOS 130 nm N-well technology operated at 1.8 V power supply voltage. The ADC consumes 2.32mW with a resolution of 6-bits for input signal frequencies upto 1 GHz and occupies a silicon area of 0.226 mm2. The operating speed of the design is 10 GHz and the simulated static INL and DNL is found to remain within 0.15LSB and 0.42LSB respectively.
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Krishna, K.L., Al-Naamani, Y.M.A., Anuradha, K. (2018). A High Speed Two Step Flash ADC. In: Zelinka, I., Senkerik, R., Panda, G., Lekshmi Kanthan, P. (eds) Soft Computing Systems. ICSCS 2018. Communications in Computer and Information Science, vol 837. Springer, Singapore. https://doi.org/10.1007/978-981-13-1936-5_84
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DOI: https://doi.org/10.1007/978-981-13-1936-5_84
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