Abstract
Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and searches that data parallel within a single clock cycle. Conventional CAM operates in three phases which are writing the binary data in the memory, pre-charging, and evaluating the match line (ML). Recently, it is identified that CAM with precharge ML consumes more power due to the short circuit current path. To overcome this problem, here, we proposed CAM architecture without applying precharge to ML which helps to operate CAM with low power and high performance. The precharge-free CAM works on two stages writing and evaluation. This paper compares conventional precharge-based ML architecture like NOR CAM and master-slave CAM of 1 (word) \(\times \) 8 (bits) with a proposed design for power consumption at different mismatches. Simulations results show that when compared to conventional designs, the proposed design minimizes approximately from 86 to 88% of average power.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Cai Z et al (2013) A distributed TCAM coprocessor architecture for integrated longest prefix matching, policy filtering, and content filtering. IEEE Trans Comput 62(3):417–427
Arsovski I, Ali S (2003) A current-saving match-line sensing scheme for content-addressable memories. In: 2003 IEEE international solid-state circuits conference (ISSCC). Digest of technical papers. IEEE
Shin Y-C et al. (1992) A special-purpose content addressable memory chip for real-time image processing. IEEE J Solid-State Circuits 27(5):737–744
Bremler-Barr A, Hendler D (2012) Space-efficient TCAM-based classification using gray coding. IEEE Trans Comput 61(1):18–30
Maurya SK, Clark LT (2011) A dynamic longest prefix matching content addressable memory for IP routing. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(6):963–972
Noda H et al (2005) A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J Solid-State Circuits 40(1):245–253
Agrawal B, Sherwood T (2008) Ternary CAM power and delay model: extensions and uses. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(5):554–564
Schultz KJ (1997) Content-addressable memory core cells a survey. Integr VLSI J 23(2):171–188
Pagiamtzis K, Sheikholeslami A (2006) Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE J Solid-State Circuits 41(3):712–727
Kittur HM (2016) Precharge-free, low-power content-addressable memory. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(8):2614–2621
Chang Y-J, Wu T-C (2015) Master-slave match line design for low-power content-addressable memory. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(9):1740–1749
Mahendra TV, Sandeep M, Anup D (2017) Self-controlled high-performance precharge-free content-addressable memory. IEEE Trans Very Large Scale Integr (VLSI) Syst
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Satyanarayana, S.V.V., Sriadibhatla, S. (2019). Efficient Precharge-Free CAM Match-Line Architecture Design for Low Power. In: Panda, G., Satapathy, S., Biswal, B., Bansal, R. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 521. Springer, Singapore. https://doi.org/10.1007/978-981-13-1906-8_17
Download citation
DOI: https://doi.org/10.1007/978-981-13-1906-8_17
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-1905-1
Online ISBN: 978-981-13-1906-8
eBook Packages: EngineeringEngineering (R0)