Abstract
This paper discusses the design and analysis of two-stage CMOS operational amplifier. This design is operated at the supply of 1.5 V in 90 nm CMOS technology. In this design, 75.17 dB open-loop gain is achieved and having 7.73 MHz unity gain bandwidth and 148.8 m degree phase margin. This circuit has 10 pF capacitive load with 0.14 nW average power dissipation and slew rate is 0.25 V/μs. This proposed circuit is designed and simulated in cadence UMC 90 nm technology.
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Acknowledgements
The authors are heartily thankful to Dr. S. Pal, Head, Department of ECE and Dr. M. K. Mishra, Vice-Chancellor, BIT Mesra for their constant encouragement and providing the suitable laboratory to carry out this research.
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Nidhi, N., Prasad, D., Nath, V. (2019). A High-Performance Energy-Efficient 75.17 dB Two-Stage Operational Amplifier. In: Nath, V., Mandal, J. (eds) Nanoelectronics, Circuits and Communication Systems . Lecture Notes in Electrical Engineering, vol 511. Springer, Singapore. https://doi.org/10.1007/978-981-13-0776-8_43
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DOI: https://doi.org/10.1007/978-981-13-0776-8_43
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