An Efficient Pipelined Feedback Processor for Computing a 1024-Point FFT Using Distributed Logic

Abstract

This paper proposes an effective fast Fourier transform (FFT) processor for 1024-point computation based on the radix-2 of decimation-in-frequency (R2DIF) and uses the pipelined feedback (PF) technique via shift registers to efficiently share the same storage between the inputs and outputs during computation. The large memory footprint of the complex twiddle factor multipliers, and hence, area on a chip, of the proposed design is reduced by employing the coordinate rotation digital computer (CoRDiC), which replaces the complex multipliers and does not require memory blocks to store the twiddle factors. To enhance the efficient usage of the hardware resources, the proposed design only uses distributed logic. This can eliminate the use of dedicated functional blocks, which are usually limited to the target chip. The entire proposed system is mapped on a Virtex-7 field-programmable gate array (FPGA) for functional verification and synthesis. The achieved result is the proposed FFT processor more effective in terms of the speed, precision, and resource, as shown in experimental results.