Abstract
Modular exponentiation is one of the core operations in most of the public-key cryptosystems. It consists of a sequence of modular multiplications. The performance of public-key cryptographic transformations is strongly influenced by the competent implementation of modular exponentiation and modular multiplication. This paper presents the hardware implementation of modular exponentiation on two processor cores. Montgomery multiplication method is modified according to the needs of dual-core implementation to improve the core utilization. It is implemented with different radices ranging from \(2^2\) to \(2^{32}\). The performance of the proposed design is analyzed and compared with the existing techniques in terms of number of clock cycles, throughput, power, and area. The proposed design has been developed using Verilog and synthesized using Xilinx-14.6 ISE for usage in FPGA, and the same has been synthesized using Cadence for ASIC. But here the results are presented based on FPGA.
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Vollala, S., Ramasubramanian, N., Shameedha Begum, B., Joshi, A.D. (2019). Dual-Core Implementation of Right-to-Left Modular Exponentiation. In: Sa, P., Bakshi, S., Hatzilygeroudis, I., Sahoo, M. (eds) Recent Findings in Intelligent Computing Techniques . Advances in Intelligent Systems and Computing, vol 707. Springer, Singapore. https://doi.org/10.1007/978-981-10-8639-7_5
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