Abstract
In this paper, we are designing an efficient memory using LVCMOS and HSTL-I IO Standards on 28 nm (Artix-7) FPGA. There are various families, LVCMOS and HSTL-I families are compared for finding the maximum power-efficient IO standards between them. We tested 64-bit RAM circuit at different range of frequencies of Intel Processor that are at Intel I-3 5005U 2.0 GHz, Intel I-3, 5015U 2.1 GHz, Intel I-3 5157U 2.5 GHz, Intel I-5 3380M 2.9 GHz, Intel I-5 3340U 3.1 GHz, and Intel I-7 3370K 3.5 GHz frequency range to find the most power-efficient circuit. When we migrate our design to LVCMOS from HSTL, then there is 40–60% saving in power dissipation of memory circuits.
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Agrawal, T., Srivastava, V. (2018). Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA. In: Muttoo, S. (eds) System and Architecture. Advances in Intelligent Systems and Computing, vol 732. Springer, Singapore. https://doi.org/10.1007/978-981-10-8533-8_10
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DOI: https://doi.org/10.1007/978-981-10-8533-8_10
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