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Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

Modular inversion is a very common primitive used for the cryptographic computations. It is the most computation intensive unit which demands more resources as compared to other primitives. Inside the modular inversion arithmetic circuits, considerable speed up with optimized architecture is required. This paper proposes an optimized parallel architecture for Itoh-Tsujii modular inversion algorithm for the field GF(2256) by introducing 23 blocks. The comparative results with conventional architecture show the 30% reduction in LUT requirement with 37% in combinational delay.

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References

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Author information

Authors and Affiliations

  1. Visvesvaraya National Institute of Technology, Nagpur, India

    Pravin Zode & R. B. Deshmukh

  2. Yeshwantrao Chavan College of Engineering, Nagpur, India

    Abdus Samad

Authors
  1. Pravin Zode
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  2. R. B. Deshmukh
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  3. Abdus Samad
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Corresponding author

Correspondence to Pravin Zode .

Editor information

Editors and Affiliations

  1. Indian Institute of Technology Roorkee, Roorkee, India

    Brajesh Kumar Kaushik

  2. Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

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Zode, P., Deshmukh, R.B., Samad, A. (2017). Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_5

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_5

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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