Abstract
In modern integrated chips, most of the power consumption comes from the memory blocks. These memory blocks require high rail voltages due to limited noise margins. Hence, the aim of this work is to design an assist circuitry which allows reduction in the retention voltage and consequently reduces the power consumption of memory. We initially designed a stable SRAM cell in 65 nm CMOS technology along with read and write assist circuits. These assist circuits enabled reduction of operating voltages. Transient Voltage Collapse Write Assist (TVC-WA) improves the writability of the SRAM cell by reducing write latency by 44% and Worldline Under Drive Read Assist (WLUD-RA) allows improvement in read stability. Both the circuits allow reduction in the supply voltage of SRAM, thereby reducing its power dissipation.
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Rehani, A., Deb, S., Shukla, S. (2017). Enhancing Retention Voltage for SRAM. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_40
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DOI: https://doi.org/10.1007/978-981-10-7470-7_40
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