Abstract
The intent of this paper is to design VLSI architectures for different CRC polynomial equations to achieve high throughput and low latency using DSP algorithms for signal processing. These architectures for CRC polynomials are designed using different techniques such a serial architecture, combined pipelining and parallelism, retiming technique, unfolding technique, and folding transformation. Linear Feedback Shift Register (LFSR) is an important component used in designing these architectures. A new formulation IIR filter-based design is proposed for designing these serial and parallel architectures using LFSR. In this paper, serial architectures, different levels of parallelism like one-level parallelism, two-level parallelisms, and three-level parallelisms are proposed for CRC-16 polynomial equation. Comparison is done between throughput and latency for different CRC polynomials for serial architectures and different levels of parallelism architectures. These architectures are designed and implemented in Verilog language and synthesized using Xilinx tool, cadence tool, etc.
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References
C. Cheng, K. K. Parhi, “High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures,” Proc. of 43rd Asilomar Conf. on Signals, Systems, and Computers, Nov. 2009, Monterey, CA, pp. 713–717.
J. H. Derby, “High Speed CRC computation using state-space transformation,” in Proc. Global Telecomm. Conf. 2001, GLOBECOM’01, vol. 1, pp. 166–170.
X. Zhang and K. K. Parhi, “High-speed architectures for parallel long BCH encoders,” in Proc. ACM Great Lakes Symp. VLSI, Boston, MA, April 2004, pp. 1–6.
Manohar Ayinala, K. K. Parhi, “Efficient Parallel VLSI Architecture for Linear Feedback Shift Registers”, IEEE Workshop on SiPS, pp. 52–57, Oct. 2010.
G. Campobello, G. Patane, and M. Russo, “Parallel CRC Realization,” IEEE Trans. Computers, vol. 52, no. 10, pp. 1312–1319, Oct 2003.
K. K. Parhi, “Eliminating the fan-out bottleneck in parallel long BCH encoders”, IEEE Transactions on Circuits and Systems I, Reg. Papers, vol. 51, no. 3, pp. 512–516, Mar. 2004.
C. Cheng, K. K. Parhi, “High Speed Parallel CRC Implementation based on Unfolding, Pipelining, Retiming,” IEEE Transaction on Circuits and Systems II, Express Briefs, vol. 53, no. 10, pp. 1017–1021, Oct. 2006.
M. Surya Prakash, Rafi Ahamed Shaik, “Low-Area and High-Throughput Architecture for an Adaptive Filter using Distributed Arithmetic”, IEEE Trans. Circuits and Systems II, Vol. 60, No. 11, pp. 781–785, Nov. 2013.
Y. Liu and K.K. Parhi, “Architectures for Recursive Digital Filters Using Stochastic Computing,” IEEE Transactions on Signal Processing, 64(14), pp. 3705–3718, July 15, 2016.
M. Ayinala, M.J. Brown and K.K. Parhi, “Pipelined Parallel FFT Architectures via Folding Transformation”, IEEE Trans. VLSI Systems, pp. 1068–1081, 20(6), June 2012.
M. Ayinala and K.K. Parhi, “High-Speed Parallel Architectures for Linear Feedback Shift Registers”, IEEE Trans. Signal Processing, 59(9), pp. 4459–4469, Sept. 2011.
M. Garrido, K.K. Parhi, and J. Grajal, “A Pipelined FFT Architecture for Real-Valued Signals”, IEEE Trans. Circuits and Systems-I: Regular Papers, 56(12), pp. 2634–2643, Dec. 2009.
C. Cheng and K.K. Parhi, “Hardware-Efficient Low-Latency Architecture for High-Throughput Rate Viterbi Decoders”, IEEE Trans. Circuits and Systems-II: Express Briefs, 55(12), pp. 1254–1258, Dec. 2008.
C. Cheng and K.K. Parhi, “High-Throughput VLSI Architecture for FFT Computation”, IEEE Trans. Circuits and Systems-II: Express Briefs, 54(10), pp. 863–867, Oct. 2007.
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Ashok Chaitanya Varma, R., Apparao, Y.V. (2018). High-Throughput VLSI Architectures for CRC-16 Computation in VLSI Signal Processing. In: Anguera, J., Satapathy, S., Bhateja, V., Sunitha, K. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 471. Springer, Singapore. https://doi.org/10.1007/978-981-10-7329-8_3
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DOI: https://doi.org/10.1007/978-981-10-7329-8_3
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