Abstract
Uniqueness is the key to go forward and maintain a spirited advantage in high-end research. By means of interdisciplinary research from the theory of very large-scale integration to signal processing prospective, it provides a systematic approach to the design and analysis of various circuits that are mainly intended for a variety of VLSI signal processing applications. This work presents an efficient design and implementation of n-bit pipelined square root circuit. An idea of a square root circuit with using a controlled subtract-multiplex (CSM) block is introduced here. In this paper, we have implemented a popular algorithm called non-restoring algorithm for the square root operation of circuits. Anticipated to meet the various design of higher order circuits to use in a range of mathematical operations, this paper provides full exposure to the researchers in the field of VLSI design. Overall, it explores the key themes of designing the square root circuit, its simulation and debugging in Xilinx ISE 14.1 as well as its FPGA implementation
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My sincere thanks to Centurion University of Technology & Management, Jatni, Bhubaneswar, Odisha for providing a high-end research platform.
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Panda, S.K., Jena, A., Panda, D.C. (2018). N-bit Pipelined CSM Based Square Root Circuit for Binary Numbers. In: Saeed, K., Chaki, N., Pati, B., Bakshi, S., Mohapatra, D. (eds) Progress in Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 564. Springer, Singapore. https://doi.org/10.1007/978-981-10-6875-1_51
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DOI: https://doi.org/10.1007/978-981-10-6875-1_51
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