Skip to main content

On Bypassing Page Cache for Block Devices on Storage Class Memory

  • Conference paper
  • First Online:
Advanced Multimedia and Ubiquitous Engineering (FutureTech 2017, MUE 2017)

Abstract

The class of memory technologies with best features from memory and storage are called storage-class memory or SCM. In the hybrid usage model of SCM, it is physically attached to the memory bus just like DRAM but it is logically shown as a block device just like a storage. In this paper, we question the effectiveness of the page cache in the hybrid model, because SCM has the read and write performance comparable to DRAM. Therefore, I implemented a way to bypass the page cache in the Linux kernel, and show the effectiveness the page cache by thorough experiments with various file I/O benchmarks.

This work was supported by the Sun Moon University Research Grant of 2014.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Simpson, R.E., Fons, P., Kolobov, A.V., Fukaya, T., Krbal, M., Tominaga, J.: Interfacial phase change memory. Nat. Nanotechnol. 6, 501–505 (2011)

    Article  Google Scholar 

  2. Chen, E., Apalkov, D., Diao, Z., et al.: Advances and future prospects of spin-transfer torque random access memory. IEEE Trans. Magn. 46(6), 1873–1878 (2010)

    Article  Google Scholar 

  3. Xue, C.J, Zhang, Y., Chen, Y., Sun, G., Yang, J.J., Li, H.: Emerging non-volatile memories: opportunities and challenges. In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS) (2011)

    Google Scholar 

  4. Dhiman, G., Ayoub, R., Rosing, T.: PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of the Design Automation Conference (DAC) (2009)

    Google Scholar 

  5. Qureshi, M., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the International Symposium on Computer Architecture (ISCA), Austin, TX (2009)

    Google Scholar 

  6. Meza, J., Chang, J., Yoon, H., Mutlu, O., Ranganathan, P.: Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management. IEEE Comput. Archit. Lett. 11(2), 61–64 (2012)

    Article  Google Scholar 

  7. Lee, B.C., Ipek, E., Mutlu, O., Burger, D.: Architecting phase change memory as a scalable DRAM alternative. In: Proceedings of the International Symposium on Computer Architecture (ISCA), Austin, TX (2009)

    Google Scholar 

  8. Bailey, K., Ceze, L., Gribble, S.D., Levy, H.M.: Operating system implications of fast, cheap, non-volatile memory. In: Proceedings of the Workshops on Hot Topics in Operating Systems (HotOS) (2011)

    Google Scholar 

  9. Mogul, J.C., Argollo, E., Shah, M., Faraboschi, P.: Operating system support for NVM + DRAM hybrid main memory. In: Proceedings of the Workshops on Hot Topics in Operating Systems (HotOS) (2009)

    Google Scholar 

  10. Meza, J., Luo, Y., Khan, S., Zhao, J., Xie, Y., Mutlu, O.; A case for efficient hardware/software cooperative management of storage and memory. In: Proceedings of the Workshop on Energy-Efficient Design (WEED) (2013)

    Google Scholar 

  11. Moraru, I., Andersen, D.G., Kaminsky, M., Tolia, N., Ranganathan, P., Binkert, N.: Consistent, durable, and safe memory management for byte-addressable non-volatile main memory. In: Proceedings of the Conference on Timely Results on Operating Systems (TRIOS) (2013)

    Google Scholar 

  12. Chen, F., Mesnier, M.P., Hahn, S.: A protected block device for persistent memory. In: Proceedings of the Symposium on Mass Storage Systems and Technologies (2014)

    Google Scholar 

  13. Tarasov, V., Zadok, E., Shepler, S.: Filebench: a flexible framework for file system benchmarking. login: USENIX Mag. 41(1), Spring 2016

    Google Scholar 

  14. Lameter, C.: Limit the size of the page cache. LWN.net, January 2007. https://lwn.net/Articles/218890

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Jin Baek Kwon .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Nature Singapore Pte Ltd.

About this paper

Cite this paper

Kwon, J.B. (2017). On Bypassing Page Cache for Block Devices on Storage Class Memory. In: Park, J., Chen, SC., Raymond Choo, KK. (eds) Advanced Multimedia and Ubiquitous Engineering. FutureTech MUE 2017 2017. Lecture Notes in Electrical Engineering, vol 448. Springer, Singapore. https://doi.org/10.1007/978-981-10-5041-1_59

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-5041-1_59

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5040-4

  • Online ISBN: 978-981-10-5041-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics