Abstract
To meet the precision requirement of different applications and reduce latency of operation for low precision, a unified structure for IEEE-754 double-precision/SIMD single-precision floating-point division and square root operation based on SRT-8 algorithm was introduced. Special instructions were designed and independent mantissa computing unit and normalization unit are implemented. Moreover, parallel adders and QDS structure was adopted to hide the latency of look-up table, generating fast addend was used to decrease critical path, and “On-the-fly” conversion was employed for saving area-cost. Experimental results show that our proposed design can achieve low latency and low hardware overhead.
This work is supported by the Aerospace Science Foundation of China (No. 2013ZC88003), and the Natural Science Foundation of China (No. 61402499).
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Peng, Y., He, T., Lei, Y., Zhu, B. (2016). Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithm. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_1
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DOI: https://doi.org/10.1007/978-981-10-3159-5_1
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