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Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering

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Information Science and Applications (ICISA) 2016

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 376))

Abstract

Despite the importance of Model Based System Engineering (MBSE) for early design verification, it is always challenging to represent the system properties / constraints at higher abstraction level due to complex behavioral and temporal aspects of embedded systems. To manage this, OCL (Object Constraint Language) and CCSL (Clock Constraint Specification Language) have been frequently used. On the other hand, SystemVerilog is a renowned hardware design and verification language that supports Assertion Based Verification (ABV). However, no real efforts have been made to employ SystemVerilog Assertions (SVA’s) in MBSE. In this paper, we explore various possibilities to represent SVA’s at higher abstraction level. Firstly, we evaluate the existing property specification approaches to represent SVA’s at higher abstraction level. Consequently, we select OCL as an appropriate approach. Secondly, we investigate the syntax and semantics of OCL in the context of SVA’s. The outcomes of research provide the sound platform to represent SVA’s in OCL for model-based design verification of embedded systems.

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Author information

Authors and Affiliations

  1. College of Computer and Information Systems, DCE, Umm Al-Qura University, Mecca, Saudi Arabia

    Muhammad Rashid

  2. MODEVES Project, National Science, Technology and Innovation Plan, Riyadh, Saudi Arabia

    Muhammad Waseem Anwar & Muhammad Kashif

  3. CEME, DCE, National University of Sciences and Technology, H-12, Islamabad, Pakistan

    Farooque Azam

Authors
  1. Muhammad Rashid
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  2. Muhammad Waseem Anwar
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  3. Farooque Azam
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  4. Muhammad Kashif
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Corresponding author

Correspondence to Muhammad Rashid .

Editor information

Editors and Affiliations

  1. Kyonggi University, iCatse Kyonggi University, Seongnam-si, Kyonggi-do, Korea (Republic of)

    Kuinam J. Kim

  2. Chair of IEEE CS STCOS, IBM T.J.Watson Research Center Chair of IEEE CS STCOS, Yorktown Heights, New York, USA

    Nikolai Joukov

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Rashid, M., Anwar, M.W., Azam, F., Kashif, M. (2016). Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering. In: Kim, K., Joukov, N. (eds) Information Science and Applications (ICISA) 2016. Lecture Notes in Electrical Engineering, vol 376. Springer, Singapore. https://doi.org/10.1007/978-981-10-0557-2_53

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  • DOI: https://doi.org/10.1007/978-981-10-0557-2_53

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  • Print ISBN: 978-981-10-0556-5

  • Online ISBN: 978-981-10-0557-2

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