Abstract
This paper proposed a novel all-digital pulsewidth lock loops which adopted cyclic binary pulsewidth detector and cyclic delay line mechanism. This design has reduced the circuit area of delay line length increase under lower frequency operation, and it utilizes binary pulsewidth detection to lock output pulsewidth rapidly, whose locking time costs in only 25 duty cycles. Moreover, two delay lines is adopted in the pulsewidth generation mechanism circuit, and the cyclic delay line is employed under low frequency operation, but bypassed under high frequency operation for simplifying pulsewidth generating path. The output pulsewidth 25, 50, 75 % (by setting) could be generated by shift register, and the operating frequency range is 100 MHz to 3 GHz at CMOS 90 nm process simulation.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Cheng KH, Su CW, Wu CL, Lo YL (2004) A phase-locked pulsewidth control loop with programmable duty cycle. In: IEEE AP-ASIC, pp 84–87
Han SR, Liu SI (2004) A 500-MHz–1.25-GHz fast-locking pulse width control loop with presentable duty cycle. IEEE J Solid-State Circuits 39:463–468
Jovanoviü G, Mitiü D, Stojþev M (2006) An adaptive pulsewidth control loop. IEEE Microelectron 626–629
Navidi MM, Abrishamifar A (2011) A fast lock time pulsewidth control loop using second order passive loop filters. In: IEEE ICEE, pp 1–5
Wang YM, Hu CF, Chen YJ, Wang JS (2005) An all-digital pulsewidth control loop, In: IEEE symposiums on VLSI circuits 2, pp 1258–1261
Wang YM, Wang JS (2004) An all-digital 50 % duty-cycle corrector. In: IEEE on ISCAS, pp 925–928
Gu JH, Wu JH, Gu DH, Zhang M, Shi LX (2012) All-digital wide range precharge logic 50 % duty cycle corrector. IEEE Trans VLSI Syst 20:760–764
Swathi R, Srinivas MB (2009) All-digital duty cycle correction circuit in 90 nm based on mutex. In: IEEE Computer Society annual symposium on VLSI (2009) 258–262
Weng RM, Lu YC, Liu CY (2009) A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment. In: IEEE ISCAS, pp 1301–1304
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media Singapore
About this paper
Cite this paper
Yang, PH., Chen, JM., Hong, ZM. (2016). All-Digital High-Speed Wide-Range Binary Detecting Pulsewidth Lock Loops. In: Hung, J., Yen, N., Li, KC. (eds) Frontier Computing. Lecture Notes in Electrical Engineering, vol 375. Springer, Singapore. https://doi.org/10.1007/978-981-10-0539-8_69
Download citation
DOI: https://doi.org/10.1007/978-981-10-0539-8_69
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-0538-1
Online ISBN: 978-981-10-0539-8
eBook Packages: Computer ScienceComputer Science (R0)