High Performance FinFET Based D Flip Flop Including Parameter Variation

Abstract

In present digital circuit’s leakage current controlled delay flip flops are needed significantly for circuit stability and high performance. The use of delay flip flop in finite state machine is to store the circuit state which requires low power consumption for scaled down devices. In this paper we have employed delay flip flop using FinFET design with multiple threshold technique to reduce the leakage power which targets both combinational and sequential elements. Parameter variations are also done to minimize sub-threshold leakage current in FinFET based D flip flops. The proposed circuit shows a design with the aim to increase the throughput of D flip flop in comparison to the Conventional transmission gate based D flip flop by considering minimum transistor count with reduced circuit delay and leakage power. Short channel effect gets considerably reduced due to fin structure and geometry. Simulation result shows that the proposed MTCMOS based FinFET D flip flop has the least leakage power dissipation of nearly 9.20 pW at 0.7 V supply voltage.