Abstract
Metastability is the source of many unexpected errors in synchronous circuits. Its mitigation is very well researched in this domain. In contrast, for asynchronous circuits it is normally assumed that the handshaking inhibits metastability. This is, however, only true within the timing closure of the circuit and in the absence of external faults. Metastability may well arise in asynchronous circuits when latching external input signals or when fault tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.
This work is supported by the Austrian Science Foundation (FWF, P21694).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Friedman, E.G.: Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proceedings of the IEEE 89(5), 665–692 (2001)
Naffziger, S.D., Colon-Bonet, G., Fischer, T., Riedlinger, R., Sullivan, T.J., Grutkowski, T.: The Implementation of the Itanium 2 Microprocessor. IEEE Journal of Solid-State Circuits 37(11), 1448–1460 (2002)
Nowick, S.M., Singh, M.: High-Performance Asynchronous Pipelines: An Overview. IEEE Design and Test of Computers 28(5), 8–22 (2011)
Chang, I.J., Park, S.P., Roy, K.: Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. IEEE Journal of Solid-State Circuits 45(2), 401–410 (2010)
Ginosar, R.: Fourteen Ways to Fool Your Synchronizer. In: International Symposium on Asynchronous Circuits and Systems, pp. 89–96 (2003)
Kinniment, D.: Synchronization and Arbitration in Digital Systems. Wiley (2007)
Cheng, F.-C., Ho, S.-L.: Efficient Systematic Error-Correcting Codes for Semi-Delay-Insensitive Data Transmission. In: International Conference on Computer Design, pp. 24–29 (2001)
Kleeman, L., Cantoni, A.: Metastable Behavior in Digital Systems. IEEE Design and Test of Computers 4(6), 4–19 (1987)
Chaney, T.J., Molnar, C.E.: Anomalous Behavior of Synchronizer and Arbiter Circuits. IEEE Transactions on Computers C 22(4), 421–422 (1973)
Catt, I.: Time Loss Through Gating of Asynchronous Logic Signal Pulses. IEEE Transactions on Electronic Computers EC-15(1), 108–111 (1966)
Veendrick, H.: The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate. IEEE Journal of Solid-State Circuits 15(2), 169–176 (1980)
Zhou, J., Kinniment, D.J., Dike, C.E., Russell, G., Yakovlev, A.: On-Chip Measurement of Deep Metastability in Synchronizers. IEEE Journal of Solid-State Circuits 43(2), 550–557 (2008)
Kacprzak, T., Albicki, A.: Analysis of Metastable Operation in RS CMOS Flip-Flops. IEEE Journal of Solid-State Circuits 22(1), 57–64 (1987)
Yang, S., Greenstreet, M.R.: Simulating Improbable Events. In: ACM/IEEE Design Automation Conference, pp. 154–157 (2007)
Kinniment, D.J., Bystrov, A., Yakovlev, A.: Synchronization Circuit Performance. IEEE Journal of Solid-State Circuits 37(2), 202–209 (2002)
Greenstreet, M.R.: Real-Time Merging. In: International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 186–198 (1999)
Nystroem, M., Martin, A.J.: Crossing the Synchronous-Asynchronous Divide. In: Workshop on Complexity-Effective Design (2002)
Fuchs, G., Fuegger, M., Steininger, A.: On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. In: IEEE Symposium on Asynchronous Circuits and Systems, pp. 127–136 (2009)
Mead, C., Conway, L.: Introduction to VLSI Systems. Addison-Wesley (1979)
Sparso, J., Furber, S.: Principles of Asynchronous Circuit Design - A Systems Perspective. Kluwer Academic Publishers (2001)
Sutherland, I.E.: Micropipelines. Communications of the ACM 32(6), 720–738 (1989)
Shams, M., Ebergen, J.C., Elmasry, M.I.: A Comparison of CMOS Implementations of an Asynchronous Circuits Primitive: the C-Element. In: International Symposium on Low Power Electronics and Design, pp. 93–96 (1996)
Kleeman, L., Cantoni, A.: On the Unavoidability of Metastable Behavior in Digital Systems. IEEE Transactions on Computers C-36(1), 109–112 (1987)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Polzer, T., Steininger, A., Lechner, J. (2013). Muller C-Element Metastability Containment. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_11
Download citation
DOI: https://doi.org/10.1007/978-3-642-36157-9_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36156-2
Online ISBN: 978-3-642-36157-9
eBook Packages: Computer ScienceComputer Science (R0)