Abstract
With the incessant pursuit for high performance, cost effective and power efficient processor design in recent years, how to provide performance with affordable hardware and power consumption has become an important issue. In this paper, we study and evaluate several variants on the TAgged GEometric history length (TAGE) branch predictors for better power, cost and performance portfolio, including fast-TAGE (f-TAGE), Fixed-Interleaving- TAGE (FI-TAGE), Non-Fixed-Interleaving TAGE (NFI-TAGE) and Bitflipping- Interleaving TAGE (BI-TAGE). We analyze and empirically study our proposed scheme along with the original TAGE with respect to branch prediction accuracy, critical path delay, hardware overhead and power consumption. It is shown, among the proposed variants that f-TAGE fares best, reducing critical path delay by over 20% while preserving prediction accuracy at affordable hardware and power requirements.
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Maa, YC., Yen, MH. (2013). On the Variants of Tagged Geometric History Length Branch Predictors. In: Pan, JS., Yang, CN., Lin, CC. (eds) Advances in Intelligent Systems and Applications - Volume 2. Smart Innovation, Systems and Technologies, vol 21. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35473-1_78
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DOI: https://doi.org/10.1007/978-3-642-35473-1_78
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