Skip to main content
SpringerLink
Log in

Architectural Support for Multithreading on Reconfigurable Hardware

  • Conference paper
Reconfigurable Computing: Architectures, Tools and Applications (ARC 2011)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6578))

Included in the following conference series:

Abstract

In this paper, we address organization and management of threads on a multithreading custom computing machine composed by a General Purpose Processor (GPP) and Reconfigurable Co-Processors. Our proposal to improve overall system performance is twofold. First, we provide architectural mechanisms to accelerate applications by supporting computationally intensive kernels with reconfigurable hardware accelerators. Second, we propose an infrastructure capable to facilitate thread management. The latter can be employed by, e.g., RTOS kernel services. Besides the architectural and microarchitecural extensions of the reconfigurable computing system, we also propose a hierarchical programming model. The model supports balanced and performance efficient SW/ HW co-execution of multithreading applications. Our experimental results based on real applications suggest average system speedups between 1.2 and 19.6 times and based on synthetic benchmarks, the achieved speedups are between 1.3 and 29.8 times compared to software only implementations.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Andrews, D., Niehaus, D., Jidin, R., Finley, M., Peck, W., Frisbie, M., Ortiz, J., Komp, E., Ashenden, P.: Programming models for hybrid FPGA-CPU computational components: a missing link. IEEE Micro 24, 42–53 (2004)

    Article  Google Scholar 

  2. Bailey, D.H., Barszcz, E., Barton, J.T., Browning, D.S., Carter, R.L., Fatoohi, R.A., Frederickson, P.O., Lasinski, T.A., Simon, H.D., Venkatakrishnan, V., Weeratunga, S.K.: The NAS parallel benchmarks. Tech. rep., The International Journal of Supercomputer Applications (1991)

    Google Scholar 

  3. Bondhugula, U., Devulapalli, A., Fernando, J., Wyckoff, P., Sadayappan, P.: Parallel fpga-based all-pairs shortest-paths in a directed graph. In: IPDPS (2006)

    Google Scholar 

  4. Buttlar, D., Farrell, J., Nichols, B.: PThreads Programming: A POSIX Standard for Better Multiprocessing. O’Reilly Media, Sebastopol (1996)

    Google Scholar 

  5. Chandra, R., Dagum, L., Kohr, D., Maydan, D., McDonald, J., Menon, R.: Parallel programming in OpenMP. Morgan Kaufmann Publishers Inc., San Francisco (2001)

    Google Scholar 

  6. Chandra, S., Regazzoni, F., Lajolo, M.: Hardware/software partitioning of operating systems: a behavioral synthesis approach. In: GLSVLSI 2006, pp. 324–329. ACM, New York (2006)

    Google Scholar 

  7. Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: A reconfigurable architecture for video image processing. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 482–491. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  8. Cui, J., Deng, Q., He, X., Gu, Z.: An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs. In: DATE, pp. 129–134 (2007)

    Google Scholar 

  9. Marconi, T., Lu, Y., Bertels, K., Gaydadjiev, G.N.: Online hardware task scheduling and placement algorithm on partially reconfigurable devices. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds.) ARCS 2008. LNCS, vol. 4943, pp. 306–311. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  10. Marescaux, T., Nollet, V., Mignolet, J.Y., Bartic, A., Moffat, W., Avasare, P., Coene, P., Verkest, D., Vernalde, S., Lauwereins, R.: Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integration 38(1), 107–130 (2004)

    Google Scholar 

  11. Nakano, T., Utama, A., Itabashi, M., Shiomi, A., Imai, M.: Harware implementation of a real-time operating system. In: 12th TRON Project International Symposium, pp. 34–42 (1995)

    Google Scholar 

  12. Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., Andrews, D.: HTHREADS: a computational model for reconfigurable devices. In: FPL, pp. 885–888 (2006)

    Google Scholar 

  13. Rhoads, S.: http://www.opencores.org/project,plasma

  14. Roldao, A., Constantinides, G.A.: A high throughput fpga-based floating point conjugate gradient implementation for dense matrices. ACM Trans. Reconfigurable Technol. Syst. 3(1), 1–19 (2010)

    Article  Google Scholar 

  15. Tumeo, A., Branca, M., Camerini, L., Monchiero, M., Palermo, G., Ferrandi, F., Sciuto, D.: An interrupt controller for fpga-based multiprocessors. In: ICSAMOS, pp. 82–87 (2007)

    Google Scholar 

  16. Uhrig, S., Maier, S., Kuzmanov, G.K., Ungerer, T.: Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: RAW, pp. 209–217 (2006)

    Google Scholar 

  17. Vassiliadis, S., Wong, S., Cotofana, S.D.: The MOLEN ρμ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  18. Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G.K., Panainte, E.M.: The Molen polymorphic processor. IEEE Transactions on Computers 53, 1363–1375 (2004)

    Article  Google Scholar 

  19. Walder, H., Platzner, M.: Reconfigurable hardware Operating Systems: From design concepts to realizations. In: Engineering of Reconfigurable Systems and Algorithms, pp. 284–287. CSREA Press (2003)

    Google Scholar 

  20. Wu, K., Kanstein, A., Madsen, J., Berekovic, M.: MT-ADRES: Multithreading on coarse-grained reconfigurable architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARC 2007. LNCS, vol. 4419, pp. 26–38. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  21. Zaykov, P.G., Kuzmanov, G.K., Gaydadjiev, G.N.: Reconfigurable multithreading architectures: A survey. In: SAMOS-IW, pp. 263–274 (July 2009)

    Google Scholar 

  22. Zhou, B., Qui, W., Peng, C.L.: An operating system framework for reconfigurable systems. In: CIT, pp. 781–787 (2005)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Engineering Department, Delft University of Technology, Delft, The Netherlands

    Pavel G. Zaykov & Georgi K. Kuzmanov

Authors
  1. Pavel G. Zaykov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Georgi K. Kuzmanov
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. FB 20 Informatik, Technische Universität Darmstadt, Hochschulstraße 10, 64289, Darmstadt, Germany

    Andreas Koch

  2. Intel Corp., 97006, Hillsboro, OR, USA

    Ram Krishnamurthy

  3. School of Electronics, Electrical Engineering and Computer Science, Institute of Electronics, Communications and Information Technology, Queen’s University of Belfast, Queen’s Road, BT3 9DT, Belfast, UK

    John McAllister  & Roger Woods  & 

  4. Department of Electrical and Computer Engineering, George Washington University, 801, 22nd Street NW, 20052, Washington, DC, USA

    Tarek El-Ghazawi

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Zaykov, P.G., Kuzmanov, G.K. (2011). Architectural Support for Multithreading on Reconfigurable Hardware. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_38

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-19475-7_38

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-19474-0

  • Online ISBN: 978-3-642-19475-7

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation