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A Survey of Low Power Design Techniques for Last Level Caches

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Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2018)

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Abstract

The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

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Notes

  1. 1.

    Though FLC power consumption is important, we focus on the LLC because they have not received much attention and consumes more power and area.

References

  1. Wendel, D., Kalla, R., Cargoni, R., Clables, J., Friedrich, J., Frech, R., Kahle, J., Sinharoy, B., Starke, W., Taylor, S., Weitzel, S., Chu, S.G., Islam, S., Zyuban, V.: The implementation of POWER7TM: a highly parallel and scalable multi-core high-end server processor. In: SSCC (2010)

    Google Scholar 

  2. Gammie, G., Wang, A., Mair, H., Lagerquist, R., Chau, M., Royannez, P., Gururajarao, S., Ko, U.: SmartReflex power and performance management technologies for 90 nm, 65 nm, and 45 nm mobile application processors. Proc. IEEE 98, 144–159 (2010)

    Article  Google Scholar 

  3. Agyeman, M.O., Zong, W.: An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD 2016, pp. 79–84 (2016)

    Google Scholar 

  4. Agyeman, M.O., Vien, Q.T., Ahmadinia, A., Yakovlev, A., Tong, K.F., Mak, T.S.T.: A resilient 2-D waveguide communication fabric for hybrid wired-wireless NoC design. IEEE Trans. Parallel Distrib. Syst. 28, 359–373 (2017)

    Google Scholar 

  5. Agyeman, M.O.: Optimizing heterogeneous 3D networks-on-chip architectures for low power and high performance applications. Ph.D. dissertation, Glasgow Caledonian University, UK (2014)

    Google Scholar 

  6. Bi, X., Mao, M., Wang, D., Li, H.H.: Cross-layer optimization for multilevel cell STT-RAM caches. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 1807–1820 (2017)

    Article  Google Scholar 

  7. Azad, Z., Farbeh, H., Monazzah, A.M.H., Miremadi, S.G.: An efficient protection technique for last level STT-RAM caches in multi-core processors. IEEE Trans. Parallel Distrib. Syst. 28, 1564–1577 (2017)

    Article  Google Scholar 

  8. Kurd, N.A., Bhamidipati, S., Mozak, C., Miller, J.L., Wilson, T.M., Nemani, M., Chowdhury, M.: Westmere: A family of 32nm IA processors. In: ISSCC (2010)

    Google Scholar 

  9. Awan, M.A., Petters, S.M.: Enhanced race-to-halt: a leakage-aware energy management approach for dynamic priority systems. In: 23rd Euromicro Conference on Real-Time Systems (2011)

    Google Scholar 

  10. Ofori-Attah, W.B.E., Agyeman, M.O.: Architectural techniques for improving the power consumption of NoC-based CMPS: a case study of cache and network layer. In: Emerging Network-on-Chip Architectures for Low Power Embedded Systems (2017)

    Article  Google Scholar 

  11. Dai, J., Guan, M., Wang, L.: Exploiting early tag access for reducing L1 data cache energy in embedded processors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22, 396–407 (2014)

    Article  Google Scholar 

  12. Ranjan, A., Venkataramani, S., Pajouhi, Z., Venkatesan, R., Roy, K., Raghunathan, A.: STAxCache: An approximate, energy efficient STT-MRAM cache. In: DATE Conference Exhibition (2017)

    Google Scholar 

  13. Gan, Z., Zhang, M., Gu, Z., Zhang, J.: Minimizing energy consumption for embedded multicore systems using cache configuration and task mapping. In: CyberC (2016)

    Google Scholar 

  14. Zang, W., Gordon-Ross, A.: A survey on cache tuning from a power/energy perspective. ACM Comput. Surv. 45, 32 (2013)

    Article  Google Scholar 

  15. Mittal, S.: A survey of architectural techniques for improving cache power efficiency. sustainable computing: Informatics and systems. Sustain. Comput.: Inform. Syst. (SUSCOM) 4, 33–43 (2014)

    Google Scholar 

  16. Ofori-Attah, E., Bhebhe, W., Agyeman, M.O.: Architectural techniques for improving the power consumption of NoC-based CMPS: a case study of cache and network layer. J. Low Power Electron. Appl. 7, 14 (2017)

    Article  Google Scholar 

  17. Ofori-Attah, E., Agyeman, M.O.: A survey of low power NoC design techniques. In: AISTECS 2017 (2017)

    Google Scholar 

  18. Ofori-Attah, E., Agyeman, M.O.: A survey of recent contributions on low power NoC architectures. In: Computing Conference (2017)

    Google Scholar 

  19. Artes, J.A., Ayala, J., Catthoor, F.: Survey of low-energy techniques for instruction memory organisations in embedded systems. J. Signal Process syst. 70(1), 1–19 (2013)

    Article  Google Scholar 

  20. Mittal, S., Vetter, J.S., Li, D.: A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Trans. Parallel Distrib. Syst. 26, 1524–1537 (2015)

    Article  Google Scholar 

  21. Indumathi, G., Aarthi, V.P.M.B.: Energy optimization techniques on SRAM: a survey. In: International Conference on Communication and Network Technologies (2014)

    Google Scholar 

  22. Apalkov, D., Khvalkovskiy, A., Watts, S., Nikitin, V., Tang, X., Lottis, D., Moon, K., Luo, X., Chen, E., Ong, A., Driskill-Smith, A., Krounbi, M.: Spin-transfer torque magnetic random access memory (STT-MRAM). J. Emerg. Technol. Comput. Syst. 9, 23 (2013)

    Article  Google Scholar 

  23. Noguchi, H., Kushida, K., Ikegami, K., Abe, K., Kitagawa, E., Kashiwada, S., Kamata, C., Kawasumi, A., Hara, H., Fujita, S.: A 250-mhz 256b-i/o 1-mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors. In: Symposium on VLSI Circuits (2013)

    Google Scholar 

  24. Noguchi, H., Ikegami, K., Shimomura, N., Tetsufumi, T., Ito, J., Fujita, S.: Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. In: Symposium on VLSI Circuits Digest of Technical Papers (2014)

    Google Scholar 

  25. Senni, S., Torres, L., Sassatelli, G., Bukto, A., Mussard, B.: Exploration of magnetic RAM based memory hierarchy for multicore architecture. In: IEEE Computer Society Annual Symposium on VLSI (2014)

    Google Scholar 

  26. Li, J., Xue, C.J., Xu, Y.: STT-RAM based energy-efficiency hybrid cache for CMPs. In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (2011)

    Google Scholar 

  27. Kim, N., Ahn, J., Seo, W., Choi, K.: Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2015)

    Google Scholar 

  28. Cheng, H.Y., Zhao, J., Sampson, J., Irwin, M.J., Jaleel, A., Lu, Y., Xie, Y.: Lap: Loop-block aware inclusion properties for energy-efficient asymmetric last level caches. In: ACM/IEEE 43rd Annual International ISCA (2016)

    Google Scholar 

  29. Shen, F., He, Y., Zhang, J., Jiang, N., Li, Q., Li, J.: Feedback learning based dead write termination for energy efficient STT-RAM caches. Chin. J. Electron. 26, 460–467 (2017)

    Article  Google Scholar 

  30. Safayenikoo, P., Asad, A., Fathy, M., Mohammadi, F.: Exploiting non-uniformity of write accesses for designing a high-endurance hybrid last level cache in 3D CMPs. In: IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE) (2017)

    Google Scholar 

  31. Mittal, S., Vetter, J.S.: AYUSH: Extending lifetime of SRAM-NVM way-based hybrid caches using wear-leveling. In: IEEE 23rd International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (2015)

    Google Scholar 

  32. Agarwal, S., Kapoor, H.K.: Restricting writes for energy-efficient hybrid cache in multi-core architectures. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2016)

    Google Scholar 

  33. Aluru, R.K., Ghosh, S.: Droop mitigating last level cache architecture for STTRAM. In: DATE (2017)

    Google Scholar 

  34. Sato, M., Sakai, Z., Egawa, R., Kobayashi, H.: An adjacent-line-merging writeback scheme for STT-RAM last-level caches. In: IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) (2017)

    Google Scholar 

  35. Liu, L., Chi, P., Li, S., Cheng, Y., Xie, Y.: Building energy-efficient multi-level cell STT-RAM caches with data compression. In: 22nd ASP-DAC (2017)

    Google Scholar 

  36. Park, J.J.K., Park, Y., Mahlke, S.: A bypass first policy for energy-efficient last level caches. In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (2016)

    Google Scholar 

  37. Hameed, F., Tahoori, M.B.: Architecting STT last-level-cache for performance and energy improvement. In: 17th ISQED (2016)

    Google Scholar 

  38. Manivannan, M., Papaefstathiou, V., Pericas, M., Stenstrom, P.: RADAR: Runtime-assisted dead region management for last-level caches. In: IEEE International Symposium on HPCA (2016)

    Google Scholar 

  39. Das, S., Aamodt, T.M., Dally, W.J.: SLIP: Reducing wire energy in the memory hierarchy. In: ACM/IEEE 42nd Annual on ISCA (2015)

    Google Scholar 

  40. Kurian, G., Devadas, S., Khan, O.: Locality-aware data replication in the last-level cache. In: IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) (2014)

    Google Scholar 

  41. Chaturvedi, N., Subramaniyan, A., Gurunarayanan, S.: Selective cache line replication scheme in shared last level cache. Proced. Comput. Sci. 46, 1095–1107 (2015)

    Article  Google Scholar 

  42. Chakraborty, S., Kapoor, H.K.: Static energy reduction by performance linked dynamic cache resizing. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2016)

    Google Scholar 

  43. Park, J., Lee, J., Kim, S.: A way-filtering-based dynamic logicalassociative cache architecture for low-energy consumption. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 793–805 (2017)

    Article  Google Scholar 

  44. Cheng, H.Y., Poremba, M., Shahidi, N., Stalev, I., Irwin, M.J., Kandemir, M., Sampson, J., Xie, Y.: EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors. In: IEEE/ACM ISLPED (2014)

    Google Scholar 

  45. Choi, J., Park, G.H.: NVM way allocation scheme to reduce NVM writes for hybrid cache architecture in chip-multiprocessors. IEEE Trans. Parallel Distrib. Syst. 28, 2896–2910 (2017)

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. Faculty of Art, Science and Technology, University of Northampton, Northampton, UK

    Emmanuel Ofori-Attah & Michael Opoku Agyeman

  2. South China University of Technology, Guangzhou, China

    Xiaohang Wang

Authors
  1. Emmanuel Ofori-Attah
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  2. Xiaohang Wang
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  3. Michael Opoku Agyeman
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Corresponding author

Correspondence to Michael Opoku Agyeman .

Editor information

Editors and Affiliations

  1. Technological Educational Institute of Western Greece, Antirrio, Greece

    Nikolaos Voros

  2. Ruhr-Universität Bochum, Bochum, Germany

    Michael Huebner

  3. Technological Educational Institute of Western Greece, Antirrio, Greece

    Georgios Keramidas

  4. Technische Universität Dresden, Dresden, Germany

    Diana Goehringer

  5. Technological Educational Institute of Western Greece, Antirio, Greece

    Christos Antonopoulos

  6. INESC-ID, Lisbon, Portugal

    Pedro C. Diniz

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Ofori-Attah, E., Wang, X., Agyeman, M.O. (2018). A Survey of Low Power Design Techniques for Last Level Caches. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_18

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  • DOI: https://doi.org/10.1007/978-3-319-78890-6_18

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