Abstract
Big Bang-Big Crunch (BB-BC) is an optimization method inspired by the corresponding evolutionary theory of the universe [1]. The BB-BC method is performed in two phases: in the Bing Bang phase, similarly to other Genetic Algorithms (GAs) it generates a random population of candidate solutions, while in the Big Crunch phase it shrinks these candidates around an optimal point via a center-of-mass or minimal cost approach. It has been shown that the BB-BC method outperforms classical GA algorithms for several optimization problems in terms of convergence speed. In this paper, we study the FPGA implementation of the BB-BC algorithm. We show that the BB-BC algorithm does not suffer from the design limitations of the classical GAs that impede the performance of their hardware-based accelerators. We propose an efficient fully pipelined design of both BB-BC phases that achieves significant speedup compared to the software counterpart. We also present a parallel scheme which integrates several BB-BC pipelined engines to improve system performance. The proposed FPGA architecture has been demonstrated for a typical optimization problem and implemented on a Xilinx Virtex-5 device.
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This work has been partly supported by the University of Piraeus Research Center.
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Abdoalnasir, A., Psarakis, M., Dounis, A. (2018). An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_14
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DOI: https://doi.org/10.1007/978-3-319-78890-6_14
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