Abstract
We present an algorithm that progressively generates canonical irredundant Sums Of Products (SOPs) for completely- and incompletely-specified Boolean functions using a satisfiability (SAT) solver. The progressive generation allows for real time monitoring and early termination, as well as for generation of partial SOPs for incremental applications. On the other hand, canonicity brings independence of the original representation and often yields smaller and more regular SOPs that lead to smaller circuits after algebraic factoring. Also, canonicity is key in applications such as constraint solving and random assignment generation, which traditionally rely on methods based on Binary Decision Diagram (BDD). However, in contrast with BDDs, our algorithm can relax canonicity to improve speed and scalability. In general, our method is more scalable for benchmarks with many structurally isomorphic outputs. It also improves the quality of results up to 10%, in terms of the SOP size, compared to a state-of-the-art BDD-based method. Experiments with global circuit restructuring using SAT-based SOPs show that area-delay product can be improved up to 27%, compared to global restructuring using BDD-based SOPs.
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Acknowledgements
This work is partly supported by NSF/NSA grant “Enhanced equivalence checking in cryptoanalytic applications” at University of California, Berkeley, and partly by SRC contract 2710.001 “SAT-based Methods for Scalable Synthesis and Verification”.
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Petkovska, A., Mishchenko, A., Novo, D., Owaida, M., Ienne, P. (2018). Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. In: Reis, A., Drechsler, R. (eds) Advanced Logic Synthesis. Springer, Cham. https://doi.org/10.1007/978-3-319-67295-3_8
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