Abstract
Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits’ lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flip-flops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores.
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References
Menta - embedded Programmable Logic. http://www.menta-efpga.com
Nanoxplore. http://www.nanoxplore.com
ADICSYS - eFPGA (embedded FPGA) IP. http://www.adicsys.com
Abramovici, M., Bradley, P., Dwarakanath, K.N., Levin, P., Memmi, G., Miller, D.: In: Sentovich, E. (ed.) Proceedings of DAC 2006, pp. 7–12. ACM (2006)
Wilton, S.J., Kafafi, N., Wu, J.C., Bozman, K.A., Aken’Ova, V.O., Saleh, R.: Design considerations for soft embedded programmable logic cores. IEEE J. Solid-State Circ. 40(2), 485–497 (2005)
Kuon, I., Egier, A., Rose, J.: Design, layout and verification of an FPGA using automated tools. In: Schmit, H., Wilton, S.J.E. (eds.) FPGA 2005, pp. 215–226. ACM (2005). http://doi.acm.org/10.1145/1046192.1046220
Voros, N., Rosti, A., Hübner, M. (eds.): Dynamic System Reconfiguration in Heterogeneous Platforms. LNEE, vol. 40. Springer, Heidelberg (2009)
Kafafi, N., Bozman, K., Wilton, S.J.: Architectures and algorithms for synthesizable embedded programmable logic cores. In: Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, pp. 3–11. ACM (2003)
Ova, V.A., Lemieux, G., Saleh, R.: An improved “soft” eFPGA design and implementation strategy. In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, pp. 179–182. IEEE (2005). http://dx.doi.org/10.1109/CICC.2005.1568636
Betz, V., Rose, J.: VPR: a new packing, placement and routing tool for FPGA research. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds.) FPL 1997. LNCS, vol. 1304, pp. 213–222. Springer, Heidelberg (1997). doi:10.1007/3-540-63465-7_226
Wiersema, T., Bockhorn, A., Platzner, M.: Embedding FPGA overlays into configurable systems-on-chip: ReconOS meets ZUMA. In: 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–6, December 2014
Leiserson, C.E., Saxe, J.B.: Retiming synchronous circuitry. Algorithmica 6, 5–35 (1991)
University of California Berkeley. (1992) Berkeley logic interchange format(blif). http://vlsi.colorado.edu/~vis/blif.ps
Jamieson, P., Kent, K.B., Gharibian, F., Shannon, L.: Odin 2 - an open-source verilog hdl synthesis tool for CAD research. In: FCCM 2010 (2010)
Brayton, R., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24–40. Springer, Heidelberg (2010). doi:10.1007/978-3-642-14295-6_5
Elmore, W.C.: The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19(1), 55–63 (1948)
Sidhu, R., Prasanna, V.K.: Fast regular expression matching using FPGAs. In: FCCM, ser. FCCM 2001, pp. 227–238. IEEE Computer Society (2001)
Acknowledgement
This work has been supported by the French National Research Agency under the contracts ANR-11-INSE-015 (ARDyT) and ANR-A0-AIRT-07 (B-Com).
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Bollengier, T., Lagadec, L., Najem, M., Le Lann, JC., Guilloux, P. (2017). Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_9
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