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Concealing Secrets in Embedded Processors Designs

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Smart Card Research and Advanced Applications (CARDIS 2016)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 10146))

Abstract

Side-channel analysis (SCA) attacks pose a serious threat to embedded systems. So far, the research on masking as a countermeasure against SCA focuses merely on cryptographic algorithms, and has either been implemented for particular hardware or software implementations. However, the drawbacks of protecting specific implementations are the lack of flexibility in terms of used algorithms, the impossibility to update protected hardware implementations, and long development cycles for protecting new algorithms. Furthermore, cryptographic algorithms are usually just one part of an embedded system that operates on informational assets. Protecting only this part of a system is thus not sufficient for most security critical embedded applications.

In this work, we introduce a flexible, SCA-protected processor design based on the open-source V-scale RISC-V processor. The introduced processor design can be synthesized to defeat SCA attacks of arbitrary attack order. Once synthesized, the processor protects the computation on security-sensitive data against side-channel leakage. The benefits of our approach are (1) flexibility and updatability, (2) faster development of SCA-protected systems, (3) transparency for software developers, (4) arbitrary SCA protection level, (5) protection not only for cryptographic algorithms, but against leakage in general caused by processing sensitive data.

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Acknowledgements

This work has been supported by the Austrian Research Promotion Agency (FFG) under grant number 845589 (SCALAS). This work was partially supported by the TU Graz LEAD project “Dependable Internet of Things in Adverse Environments”. The HECTOR project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 644052. This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No 681402).

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Authors and Affiliations

  1. Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Inffeldgasse 16a, 8010, Graz, Austria

    Hannes Gross, Manuel Jelinek, Stefan Mangard, Thomas Unterluggauer & Mario Werner

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  1. Hannes Gross
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  2. Manuel Jelinek
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  3. Stefan Mangard
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  4. Thomas Unterluggauer
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  5. Mario Werner
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Correspondence to Hannes Gross .

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Editors and Affiliations

  1. Bonn-Rhein-Sieg University of Applied Sciences, St. Augustin, Germany

    Kerstin Lemke-Rust

  2. Cryptography Research Inc. , San Francisco, California, USA

    Michael Tunstall

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Gross, H., Jelinek, M., Mangard, S., Unterluggauer, T., Werner, M. (2017). Concealing Secrets in Embedded Processors Designs. In: Lemke-Rust, K., Tunstall, M. (eds) Smart Card Research and Advanced Applications. CARDIS 2016. Lecture Notes in Computer Science(), vol 10146. Springer, Cham. https://doi.org/10.1007/978-3-319-54669-8_6

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  • DOI: https://doi.org/10.1007/978-3-319-54669-8_6

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  • Print ISBN: 978-3-319-54668-1

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