Abstract
In this chapter a unified architecture providing a generic, programmable, and scalable RNS computation based on {2n ± k i } moduli channels is described. This architecture allows for the design of RNS with an arbitrarily long moduli set of the form {2n ± k 0, ⋯ , 2n ± k j }, with \(j \in \mathbb{N}_{0}^{+}\). The considered moduli set allows to arbitrarily increase the number of RNS channels and consequently increasing the Dynamic Range (DR) or reducing the width of the channels, leading to a reduction in delay and area cost of the arithmetic operations, allowing to further exploit the RNS parallelism. The proposed RNS architecture provides not only a programmable processor capable of supporting a wide range of algorithms using RNS, but also a tool for researchers to evaluate new algorithms, moduli sets, and conversion approaches.
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Matutino, P.M., Chaves, R., Sousa, L. (2017). RNS-Based Embedded Processor Design. In: Molahosseini, A., de Sousa, L., Chang, CH. (eds) Embedded Systems Design with Special Arithmetic and Number Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-49742-6_2
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DOI: https://doi.org/10.1007/978-3-319-49742-6_2
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