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Locality of Computation for Stencil Optimization

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Algorithms and Architectures for Parallel Processing (ICA3PP 2016)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10048))

Abstract

Stencil computation is a performance critical kernel that is widely used in scientific and engineering applications. In this paper we develop a redundant computation elimination (RCE) algorithm to exploit temporal locality. We implement the RCE optimization strategy using ROSE compiler infrastructure. The experiments with a benchmark of eleven stencil applications show that temporal locality of RCE averagely improves performance by 15.4% and 10.1% for benchmark without or with SIMD optimization.

G.Tan —We would like to express our gratitude to all reviewers constructive comments for helping us polishing this paper. This work is supported by The National Key Research and Development Program of China (2016YFB0201305), National Science and Technology Major Project (2013ZX0102-8001-001-001) and National Natural Science Foundation of China, under grant No. (91430218, 31327901, 61472395, 61272134, 61432018).

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Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Lufeng Yuan, Junhong Liu, Yulong Luo & Guangming Tan

Authors
  1. Lufeng Yuan
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  2. Junhong Liu
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  3. Yulong Luo
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  4. Guangming Tan
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Corresponding author

Correspondence to Guangming Tan .

Editor information

Editors and Affiliations

  1. University Carlos III of Madrid, Leganes, Spain

    Jesus Carretero

  2. Carlos III University of Madrid, Leganes, Madrid, Spain

    Javier Garcia-Blas

  3. The University of Waikato, Hamilton, New Zealand

    Ryan K.L. Ko

  4. IBM Zurich Research Laboratory, Rüschlikon, Switzerland

    Peter Mueller

  5. Hiroshima University, Higashi-Hiroshima, Japan

    Koji Nakano

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Yuan, L., Liu, J., Luo, Y., Tan, G. (2016). Locality of Computation for Stencil Optimization. In: Carretero, J., Garcia-Blas, J., Ko, R., Mueller, P., Nakano, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2016. Lecture Notes in Computer Science(), vol 10048. Springer, Cham. https://doi.org/10.1007/978-3-319-49583-5_34

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  • DOI: https://doi.org/10.1007/978-3-319-49583-5_34

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-49582-8

  • Online ISBN: 978-3-319-49583-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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