Abstract
We revisit the approach to Byzantine fault-tolerant clock synchronization based on approximate agreement introduced by Lynch and Welch. Our contribution is threefold: (i) We provide a slightly refined variant of the algorithm yielding improved bounds on the skew that can be achieved and the sustainable frequency offsets. (ii) We show how to extend the technique to also synchronize clock rates. This permits less frequent communication without significant loss of precision, provided that clock rates change sufficiently slowly. (iii) We present a coupling scheme that allows to make these algorithms self-stabilizing while preserving their high precision. The scheme utilizes a low-precision, but self-stabilizing algorithm for the purpose of recovery.
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Notes
- 1.
- 2.
A prototype FPGA implementation achieves \(182\,\)ps skew [12], which is suitable for generating a system clock.
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- 4.
d tends to be at least one or two orders of magnitude larger than U.
- 5.
If a node has fewer than \(2f+1\) neighbors in a system tolerating f faults, it cannot distinguish whether it synchronizes to a group of f correct or f faulty neighbors.
- 6.
Discretization can be handled by re-interpreting the discretization error as part of the delay uncertainty. All our algorithms use the hardware clock exclusively to measure bounded time differences.
- 7.
Typically, e(r) is a monotone sequence, implying that simply \(E=\lim _{r\rightarrow \infty }e(r)\).
- 8.
Dividing the measured local time differences by \((\vartheta +1)/2\) is an artifact of our “one-sided” definition of hardware clock rates from \([1,\vartheta ]\); in an implementation, one simply reads the hardware clocks (which exhibit symmetric error) without any scaling.
- 9.
Given that hardware clock speeds may differ by at most factor \(\vartheta \), nodes need to be able to increase or decrease their rates by factor \(\vartheta \): a single deviating node may be considered faulty by the algorithm, so each node must be able to bridge this speed difference on its own.
References
Overview of Silicon Oscillators by Linear Technology (retrieved May 2016). http://cds.linear.com/docs/en/product-selector-card/2PB_osccalcfb.pdf
Daliot, A., Dolev, D.: Self-Stabilizing Byzantine Pulse Synchronization. Computing Research Repository abs/cs/0608092 (2006)
Distributed Algorithms for Robust Tick-Synchronization (2005–2008). http://ti.tuwien.ac.at/ecs/research/projects/darts. Accessed 5, 2014
Dolev, D., Függer, M., Lenzen, C., Posch, M., Schmid, U., Steininger, A.: Rigorously modeling self-stabilizing fault-tolerant circuits: an ultra-robust clocking scheme for systems-on-chip. J. Comput. Syst. Sci. 80(4), 860–900 (2014)
Dolev, D., Függer, M., Lenzen, C., Schmid, U.: Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation. J. ACM 61(5), 1–74 (2014)
Dolev, D., Halpern, J.Y., Strong, H.R.: On the possibility and impossibility of achieving clock synchronization. J. Comput. Syst. Sci. 32(2), 230–250 (1986)
Dolev, D., Lynch, N.A., Pinter, S.S., Stark, E.W., Weihl, W.E.: Reaching approximate agreement in the presence of faults. J. ACM 33, 499–516 (1986)
Dolev, S., Welch, J.L.: Self-stabilizing clock synchronization in the presence of byzantine faults. J. ACM 51(5), 780–799 (2004)
FlexRay Consortium, et al.: FlexRay communications system-protocol specification. Version 2, 1 (2005)
Függer, M., Armengaud, E., Steininger, A.: Safely stimulating the clock synchronization algorithm in time-triggered systems - a combined formal & experimental approach. IEEE Trans. Ind. Inf. 5(2), 132–146 (2009)
Függer, M., Schmid, U.: Reconciling fault-tolerant distributed computing and systems-on-chip. Distrib. Comput. 24(6), 323–355 (2012)
Huemer, F., Kinali, A., Lenzen, C.: Fault-tolerant Clock Synchronization with High Precision. In: IEEE Symposium on VLSI (ISVLSI) (2016). to appear
Kopetz, H., Bauer, G.: The time-triggered architecture. Proc. IEEE 91(1), 112–126 (2003)
Lundelius, J., Lynch, N.: An upper and lower bound for clock synchronization. Inf. Control 62(2–3), 190–204 (1984)
Schossmaier, K.: Interval-based Clock State and Rate Synchronization. Ph.D. thesis, Technical University of Vienna (1998)
Schossmaier, K., Weiss, B.: An algorithm for fault-tolerant clock state and rate synchronization. In: 18th Symposium on Reliable Distributed Systems (SRDS), pp. 36–47 (1999)
Srikanth, T.K., Toueg, S.: Optimal clock synchronization. J. ACM 34(3), 626–645 (1987)
Welch, J.L., Lynch, N.A.: A new fault-tolerant algorithm for clock synchronization. Inf. Comput. 77(1), 1–36 (1988)
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Khanchandani, P., Lenzen, C. (2016). Self-stabilizing Byzantine Clock Synchronization with Optimal Precision. In: Bonakdarpour, B., Petit, F. (eds) Stabilization, Safety, and Security of Distributed Systems. SSS 2016. Lecture Notes in Computer Science(), vol 10083. Springer, Cham. https://doi.org/10.1007/978-3-319-49259-9_18
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