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VLSI Test and Hardware Security Background for Hardware Obfuscation

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Hardware Protection through Obfuscation

Abstract

This chapter discusses the fundamental concepts of design and testing and their role in hardware obfuscation. It outlines the traditional design flow of integrated circuits and assesses the vulnerabilities associated with the verification techniques and testing structures that can expose the design details and help reverse-engineer the functionality. A survey of security enhancement schemes has been presented. Furthermore, different classifications of hardware obfuscation have been discussed that cover the associated vulnerabilities of key management in nonvolatile memories (NVMs). The review of nonvolatile memories, emerging technologies and hardware-based cryptographic primitives, physical unclonable functions (PUFs) and true random number generators (TRNGs) and their use in hardware obfuscation techniques has been deliberated.

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Author information

Authors and Affiliations

  1. Florida Institute of Technology, Melbourne, Florida, USA

    Fareena Saqib

  2. University of New Mexico, Albuquerque, NM, USA

    Jim Plusquellic

Authors
  1. Fareena Saqib
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  2. Jim Plusquellic
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Correspondence to Fareena Saqib .

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Editors and Affiliations

  1. University of Florida, Gainseville, Florida, USA

    Domenic Forte

  2. University of Florida, Gainseville, Florida, USA

    Swarup Bhunia

  3. University of Florida, Gainseville, Florida, USA

    Mark M. Tehranipoor

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Saqib, F., Plusquellic, J. (2017). VLSI Test and Hardware Security Background for Hardware Obfuscation. In: Forte, D., Bhunia, S., Tehranipoor, M. (eds) Hardware Protection through Obfuscation. Springer, Cham. https://doi.org/10.1007/978-3-319-49019-9_2

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  • DOI: https://doi.org/10.1007/978-3-319-49019-9_2

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  • Online ISBN: 978-3-319-49019-9

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