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Modulo Addition and Subtraction

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Residue Number Systems

Abstract

In this Chapter, the basic operations of modulo addition and subtraction are considered. Both the cases of general moduli and specific moduli of the form 2n−1 and 2n + 1 are considered in detail. The case with moduli of the form 2n + 1 can benefit from the use of diminished-1 arithmetic. Multi-operand modulo addition also is discussed.

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References

  1. M.A. Bayoumi, G.A. Jullien, W.C. Miller, A VLSI implementation of residue adders. IEEE Trans. Circuits Syst. 34, 284–288 (1987)

    Article  Google Scholar 

  2. M. Dugdale, VLSI implementation of residue adders based on binary adders. IEEE Trans. Circuits Syst. 39, 325–329 (1992)

    Article  MATH  Google Scholar 

  3. R.P. Brent, H.T. Kung, A regular layout for parallel adders. IEEE Trans. Comput. 31, 260–264 (1982)

    Article  MathSciNet  MATH  Google Scholar 

  4. G. Alia, E. Martinelli, Designing multi-operand modular adders. Electron. Lett. 32, 22–23 (1996)

    Article  Google Scholar 

  5. K.M. Elleithy, M.A. Bayoumi, A θ(1) algorithm for modulo addition. IEEE Trans. Circuits Syst. 37, 628–631 (1990)

    Article  Google Scholar 

  6. A.A. Hiasat, High-speed and reduced area modular adder structures for RNS. IEEE Trans. Comput. 51, 84–89 (2002)

    Article  MathSciNet  Google Scholar 

  7. C. Efstathiou, D. Nikolos, J. Kalanmatianos, Area-time efficient modulo 2n−1 adder design. IEEE Trans. Circuits Syst. 41, 463–467 (1994)

    Article  MATH  Google Scholar 

  8. R.E. Ladner, M.J. Fischer, Parallel-prefix computation. JACM 27, 831–838 (1980)

    Google Scholar 

  9. P.M. Kogge, H.S. Stone, A parallel algorithm for efficient solution of a general class of recurrence equations. IEEE Trans. Comput. 22, 783–791 (1973)

    MathSciNet  MATH  Google Scholar 

  10. S. Knowles, A family of adders, in Proceedings of the 15th IEEE Symposium on Computer Arithmetic, Vail, 11 June 2001–13 June 2001. pp. 277–281

    Google Scholar 

  11. R. Zimmermann, Efficient VLSI implementation of Modulo (2n ± 1) addition and multiplication, Proceedings of the IEEE Symposium on Computer Arithmetic, Adelaide, 14 April 1999–16 April 1999. pp. 158–167

    Google Scholar 

  12. L. Kalampoukas, D. Nikolos, C. Efstathiou, H.T. Vergos, J. Kalamatianos, High speed parallel prefix modulo (2n−1) adders. IEEE Trans. Comput. 49, 673–680 (2000)

    Article  Google Scholar 

  13. A. Tyagi, A reduced area scheme for carry-select adders. IEEE Trans. Comput. 42, 1163–1170 (1993)

    Article  Google Scholar 

  14. C. Efstathiou, H.T. Vergos, D. Nikolos, Modulo 2n ± 1 adder design using select-prefix blocks. IEEE Trans. Comput. 52, 1399–1406 (2003)

    Article  Google Scholar 

  15. R.A. Patel, S. Boussakta, Fast parallel-prefix architectures for modulo 2n−1 addition with a single representation of zero. IEEE Trans. Comput. 56, 1484–1492 (2007)

    Article  MathSciNet  Google Scholar 

  16. L.M. Liebowitz, A simplified binary arithmetic for the fermat number transform. IEEE Trans. ASSP 24, 356–359 (1976)

    Article  Google Scholar 

  17. Z. Wang, G.A. Jullien, W.C. Miller, An efficient tree architecture for modulo (2n + 1) multiplication. J. VLSI Sig. Proc. Syst. 14(3), 241–248 (1996)

    Google Scholar 

  18. H.T. Vergos, C. Efstathiou, D. Nikolos, Diminished-1 modulo 2n + 1 adder design. IEEE Trans. Comput. 51, 1389–1399 (2002)

    Article  MathSciNet  Google Scholar 

  19. S. Efstathiou, H.T. Vergos, D. Nikolos, Fast parallel prefix modulo (2n + 1) adders. IEEE Trans. Comput. 53, 1211–1216 (2004)

    Article  Google Scholar 

  20. H.T. Vergos, C. Efstathiou, A unifying approach for weighted and diminished-1 modulo (2n + 1) addition. IEEE Trans. Circuits Syst. II Exp. Briefs 55, 1041–1045 (2008)

    Article  Google Scholar 

  21. H.T. Vergos, D. Bakalis, On the use of diminished-1 adders for weighted modulo (2n + 1) arithmetic components, Proceedings of the 11th Euro Micro Conference on Digital System Design Architectures, Methods Tools, Parma, 3–5 Sept. 2008. pp. 752–759

    Google Scholar 

  22. S.H. Lin, M.H. Sheu, VLSI design of diminished-one modulo (2n + 1) adders using circular carry selection. IEEE Trans. Circuits Syst. 55, 897–901 (2008)

    Article  Google Scholar 

  23. T.B. Juang, M.Y. Tsai, C.C. Chin, Corrections to VLSI design of diminished-one modulo (2n + 1) adders using circular carry selection. IEEE Trans. Circuits Syst. 56, 260–261 (2009)

    Article  Google Scholar 

  24. T.-B. Juang, C.-C. Chiu, M.-Y. Tsai, Improved area-efficient weighted modulo 2n + 1 adder design with simple correction schemes. IEEE Trans. Circuits Syst. II Exp. Briefs 57, 198–202 (2010)

    Article  Google Scholar 

  25. J. Sklansky, Conditional sum addition logic. IEEE Trans. Comput. EC-9, 226–231 (1960)

    Article  MathSciNet  Google Scholar 

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Ananda Mohan, P.V. (2016). Modulo Addition and Subtraction. In: Residue Number Systems. Birkhäuser, Cham. https://doi.org/10.1007/978-3-319-41385-3_2

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