Abstract
In this work we present a methodology to design the next generation of real-time vision processors. These processors are expected to achieve high throughput with complex applications, under real-time embedded constraints (time, fault-tolerance, silicon area and power consumption). To achieve these goals, we propose the fusion of two key concepts: the Focal-Plane Image Processing (FPIP) and the Many-Core architectures. We show the concepts and ideas to build-up a methodology able to offer both design space exploration, and a customized programming toolchain for the final architecture. We present implementation details and results for working parts of the framework, and partial results and general comments about the work-in-progress.
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Acknowledgment
The authors would like to acknowledge CAPES Foundation/Brazilian Ministry of Education (Science without Borders Program, Grant Process Nr. 9054-13-8) and the support received from the University of Brasilia.
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Mori, J.Y., Werner, A., Shallufa, A., Fricke, F., Hübner, M. (2016). A Design Methodology for the Next Generation Real-Time Vision Processors. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_2
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DOI: https://doi.org/10.1007/978-3-319-30481-6_2
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