Skip to main content

A General Methodology to Design Deadlock-Free Routing Algorithms for Mesh Networks

  • Conference paper
  • First Online:
Algorithms and Architectures for Parallel Processing (ICA3PP 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9528))

Abstract

This paper presents a general methodology to design deadlock-free routing algorithms for mesh networks. Classifying directions of the network channels, constructing deadlock-free zones, and arranging the produced deadlock-free zones in a specific order are the three fundamental steps that the proposed methodology takes to generate connected and deadlock-free routing algorithms. Applying the proposed methodology to 2-D mesh network, we generate eighty two routing algorithms: some of them (such as dimension order routing, turn model) have already been proposed in the literature; while most of them have not been proposed before. Furthermore, the methodology reveals the relation among the previously reported routing algorithms proposed in different papers. Extensive simulation experiments have been performed for nine selected routing algorithms, considering various traffic patterns, different network sizes, various buffer sizes, and a wide range of injection rates. Results show that for a given network the performance of a routing algorithm mainly depends on the traffic pattern.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    See Sect. 6 for detail.

References

  1. Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.: An 80-tile sub-100-W teraflops processor in 65-nm CMOS. IEEE J. Solid-State Circuits 43(1), 29–41 (2008)

    Article  Google Scholar 

  2. Bell, S., Edwards, B., Amann, J., Conlin, R., Joyce, K., Leung, V., MacKay, J., Reif, M., Bao, L.W., Brown, J., Mattina, M., Miao, C.C., Ramey, C., Wentzlaff, D., Anderson, W., Berger, E., Fairbanks, N., Khan, D., Montenegro, F., Stickney, J., Zook, J.: Tile64-processor: a 64-core SoC with mesh interconnect. In: International Solid-State Circuits Conference, pp. 88–89,598. IEEE Press, New York (2008)

    Google Scholar 

  3. Marculescu, R., Ogras, U.Y., Peh, L.S., Jerger, N.E., Hoskote, Y.: Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans. CAD Integr. Circ. Syst. 28(1), 3–21 (2009)

    Article  Google Scholar 

  4. Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)

    Google Scholar 

  5. Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: An Engineering Approach. IEEE Press, New York (1997)

    Google Scholar 

  6. Duato, J.: A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parallel Distrib. Syst. 4(12), 1320–1331 (1993)

    Article  Google Scholar 

  7. Towles, B., Grossman, J.P., Greskamp, B., Shaw, D.E.: Unifying on-chip and inter-node sitching within the Anton 2 network. In: International Symposium on Computer Architecuture (ISCA), pp. 1–12. IEEE Press, New York (2014)

    Google Scholar 

  8. Glass, C.J., Ni, L.: The turn model for adaptive routing. J. ACM 41(5), 874–902 (1994)

    Article  Google Scholar 

  9. Chiu, G.M.: The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)

    Article  Google Scholar 

  10. Boura, Y.M., Das, C.R.: Efficient fully adaptive wormhole routing in n-dimensional meshes. In: International Conference on Distributed Computing Systems, pp. 589–596. IEEE Press, New York (1994)

    Google Scholar 

  11. Palesi, M., Holsmark, R., Kumar, S., Catania, V.: Application specific routing algorithms for networks on chip. IEEE Trans. Parallel Distrib. Syst. 20(3), 316–330 (2009)

    Article  Google Scholar 

  12. Glass, C.J., Ni, L.M.: Maximally fully adaptive routing in 2D meshes. In: International Conference on Parallel Processing, pp. 101–104. IEEE Press, New York (1992)

    Google Scholar 

  13. Fu, B., Han, Y.H., Li, H.W.: An abacus turn model for time/space-efficient reconfigurable routing. In: International Symposium on Computer Architecture (ISCA), pp. 259–270. ACM Press, New York (2011)

    Google Scholar 

  14. Linder, D.H., Harden, J.C.: An adaptive and fault-tolerant wormhole routing strategy for k-ary n-cubes. IEEE Trans. Comput. 40(1), 2–12 (1991)

    Article  MathSciNet  Google Scholar 

  15. Chien, A., Kim, J.H.: Planar-adaptive routing: low-cost adaptive networks for multiprocessors. J. ACM 42(1), 91–123 (1995)

    Article  MATH  Google Scholar 

  16. Xiang, D.: Deadlock-free adaptive routing in meshes with fault-tolerance ability using channel overlapping. IEEE Trans. Dependab. Sec. Comput. 8(1), 74–88 (2011)

    Article  Google Scholar 

  17. Luo, W., Xiang, D.: An efficient adaptive deadlock-free routing algorithm for torus networks. IEEE Trans. Parallel Distrib. Syst. 23(5), 800–808 (2012)

    Article  Google Scholar 

  18. Xiang, D., Zhang, Y.L., Pan, Y.: Practical deadlock-free fault-tolerant routing in meshes based on the planar network fault model. IEEE Trans. Comput. 58(5), 620–633 (2009)

    Article  MathSciNet  Google Scholar 

  19. Ma, S., Wang, Z., Jerger, N.E., Shen, L., Xiao, N.: Novel flow control for fully adaptive routing in cache-coherent NoCs. IEEE Trans. Parallel Distrib. Syst. 25(9), 2397–2407 (2014)

    Article  Google Scholar 

  20. Alonso, M.G., Xiang, D., Flich, J., Yu, Z.G., Duato, J.: Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm. In: International Symposium on Networks-on-Chip, pp. 25–32. IEEE Press, New York (2014)

    Google Scholar 

  21. Scott, S., Thorson, G.: The cray T3E network: adaptive routing in a high performance 3D torus. In: High-performance Interconnects Symposium, Hot Interconnects IV, pp. 147–156. Stanford University (1996)

    Google Scholar 

  22. Moravejia, R., Sarbazi-Azadb, H., Zomayac, A.Y.: A general methodology for direction-based irregular routing algorithms. J. Parallel Distrib. Comput. 70(5), 270–363 (2010)

    Google Scholar 

  23. Wang, X.Y., Xiang, D., Yu, Z.G.: TM: a new and simple topology for interconnection networks. J. Supercomput. 66(1), 514–538 (2013)

    Article  Google Scholar 

  24. http://www.top500.org/

  25. Xie, M., Lu, Y., Wang, K., Cao, H., Yang, X.: Tianhe-1A interconnect and message-passing services. IEEE Micro 32(1), 8–20 (2012)

    Article  Google Scholar 

  26. Adiga, N.R., Blumrich, M.A., Chen, D., Coteus, P., Gara, A., Giampapa, M.E., Heidelberger, P., Singh, S., Steinmacher-Burow, B.D., Takken, T., Tsao, M., Vranas, P.: Blue gene/L torus interconnection network. IBM J. Res. Dev. 49, 265–276 (2005)

    Article  Google Scholar 

  27. Yu, Z.G., Xiang, D., Wang, X.Y.: Balancing virtual channel utilization for deadlock-free routing in torus networks. J. Supercomput. 71(8), 3094–3115 (2015)

    Article  Google Scholar 

  28. Verbeek, F., Schialtz, J.: On necessary and sufficient conditions for deadlock-free routing in wormhole networks. IEEE Trans. Parallel Distrib. Syst. 22(10), 2022–2032 (2011)

    Article  Google Scholar 

Download references

Acknowledgements

We sincerely thank the anonymous reviewers for their helpful comments and suggestions. This work is supported by the National Science Foundation of China under grants 61171121, 61402086, 61572279 and Scientific Research Foundation of Liaoning Provincial Education Department (No. L2015165), and DUFE Excellent Talents Project (No. DUFE2015R06).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Zhigang Yu .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this paper

Cite this paper

Yu, Z., Wang, X., Shen, K., Liu, H. (2015). A General Methodology to Design Deadlock-Free Routing Algorithms for Mesh Networks. In: Wang, G., Zomaya, A., Martinez, G., Li, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2015. Lecture Notes in Computer Science(), vol 9528. Springer, Cham. https://doi.org/10.1007/978-3-319-27119-4_33

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-27119-4_33

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-27118-7

  • Online ISBN: 978-3-319-27119-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics