Skip to main content

Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits

  • Chapter
Secure System Design and Trustable Computing

Abstract

Counterfeit integrated circuits (ICs) have been on the rise over the past decade and represent a major concern. Counterfeits impact the security and reliability of electronic systems particularly those deployed in critical applications. While there are several different types of counterfeit ICs in the supply chain (cloned, recycled, remarked, overproduced, etc.), reports indicate that recycled ICs constitute the majority of all counterfeit ICs in the market today. Such ICs are recovered from the scrapped boards of used devices. Since these ICs are identical to their unused counterparts in appearance, functionality, and packaging, detecting them can be challenging. It has been observed that path delays in recycled ICs will be larger than those in unused ICs due to the effects of silicon aging, such as negative/positive bias temperature instability (NBTI/PBTI) and hot carrier injection (HCI). In this chapter, a circuit timing signature (CTS) technique is presented to distinguish recycled ICs from unused ones. Specifically, a clock sweeping technique is employed both to measure the amount of path delay and to generate a timing signature for chips under testing. Due to the degradation in the field, the path delay distribution of recycled ICs becomes different from that of new/unused ICs, resulting in a different CTS. An authentication flow for accurately identifying recycled ICs is presented. Results show that statistical analysis can effectively separate the impact of process variations from aging effects on path delay. In addition, the CTS is extended to the detection of cloned ICs, overproduced ICs, and remarked ICs. A unique binary ID is generated based on the CTS of each IC. By checking the intrinsic IDs, cloned, overproduced, and remarked ICs can be effectively identified.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Trust-HUB.: (2010). http://trust-hub.org/home

  2. Cassell, J.: Reports of counterfeit parts quadruple since 2009. Challenging US Defence Industry and National Security

    Google Scholar 

  3. U.S. Senate Committee on Armed Services.: Inquiry into counterfeit electronic parts in the department of defence supply chain (2012)

    Google Scholar 

  4. U.S. Senate Committee on Armed Services.: Suspect counterfeit electronic parts can be found on internet purchasing platforms (2012)

    Google Scholar 

  5. US Congress.: National Defense Authorization Act for Fiscal Year (2012)

    Google Scholar 

  6. Guin, U., DiMase, D., Tehranipoor, M.: A comprehensive framework for counterfeit defect coverage analysis and detection assessment. J. Electron. Test. Theory Appl. (JETTA) 30(1), 25–40 (2014)

    Google Scholar 

  7. US, Department of Commerce.: Defense industrial base assessment: counterfeit electronics (2010)

    Google Scholar 

  8. Guin, U., Forte, D., Tehranipoor, M.: Anti-counterfeit techniques: from design to resign. In: IEEE Microprocessor Test Verification (MTV) (2013)

    Google Scholar 

  9. Tehranipoor, M., Koushanfar, F.: A survey of hardware Trojan taxonomy and detection. IEEE Des. Test 27(1), 10–25 (2010)

    Article  Google Scholar 

  10. Brown, S.: Lifecycle of consumer digital products (2007)

    Google Scholar 

  11. Bureau of Industry and Security, U.S. Department of Commerce.: Defense industrial base assessment: counterfeit electronics (Jan 2010)

    Google Scholar 

  12. Tehranipoor, M., Wang, C.: Introduction to Hardware Security and Trust. Springer, Berlin/Heidelberg (2011)

    Google Scholar 

  13. Zhang, X., Tuzzio, N., Tehranipoor, M.: Identification of recovered ICs using fingerprints from a light-weight on-chip sensor. In: Proceedings of Design Automation Conference (DAC) (2012)

    Google Scholar 

  14. Guin, U., Forte, D., Tehranipoor, M.: Low-cost on-chip structures for combating die and IC recycling. In: Design Automation Conference (DAC) (2014)

    Google Scholar 

  15. Huang, K., Carulli, J., Makris, Y.: Parametric counterfeit IC detection via support vector machines. In: Proceedings of International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT), pp. 7–12 (2012)

    Google Scholar 

  16. Zhang, X., Xiao, K., Tehranipoor, M.: Path-delay fingerprinting for identification of recovered ICs. In: Proceedings of International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT) (Oct 2012)

    Google Scholar 

  17. Lofstrom, K., Daasch, W.R., Taylor, D.: IC identification circuit using device mismatch. In: Proceedings ISSCC 2000 (Feb 2000)

    Book  Google Scholar 

  18. Pappu, R.: Physical one-way functions. Ph.D. Thesis, Massachusets Instutute of Tecnhology (2001)

    Google Scholar 

  19. Ozturk, E., Hammouri, G., Sunar, B.: Physical unclonable function with tristate buffers. In: Proceedings of ISCAS08, pp. 3194–3197 (2008)

    Google Scholar 

  20. Koushanfar, F., Qu, G., Potkonjak, M.: Intellectual property metering. In: Proceedings of 4th International Workshop Information Hiding, pp. 81–95 (2001)

    Google Scholar 

  21. Alkabani, Y., Koushanfar, F.: Active hardware metering for intellectual property protection and security. In: Proceedings of 16th USENIX Security Symposium, Usenix Association, pp. 291–306 (2007)

    Google Scholar 

  22. Contreras, G., Rahman, T., Tehranipoor, M.: Secure split-test for preventing IC piracy by untrusted foundry and assembly. In: Proceedings of International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT) (2013)

    Google Scholar 

  23. Tuzzio, N., Xiao, K., Zhang, X., Tehranipoor, M.: A zero-overhead IC identification technique using clock sweeping and path delay analysis. In: IEEE GLSVLSI (2012)

    Book  Google Scholar 

  24. Kimizuka, N., Yamamoto, T., Mogami, T., Yamaguchi, K., Imai, K., Horiuchi, T.: The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on mosfet scaling. In: VLSI Technology (1999)

    Book  Google Scholar 

  25. Vattikonda, R., Wang, W., Cao, Y.: Modeling and minimization of pmos nbti effect for robust nanometer design. In: Proceedings of the 43rd Annual Conference on Design Automation (DAC’06), pp. 1047–1052 (2006)

    Google Scholar 

  26. Jiang, W., Le, H., Chung, J., Kopley, T., Marcoux, P., Dai, C.: Assessing circuit-level hot-carrier reliability. In: IEEE International Reliability Physics Symposium Proceedings, pp. 173–179 (1998)

    Google Scholar 

  27. Wu, L., et al.: Glacier: a hot carrier gate level circuit characterization and simulation system for vlsi design. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 73–79 (2000)

    Google Scholar 

  28. Synopsys.: HSPICE user guide (2010)

    Google Scholar 

  29. Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall, Upper Saddle River (2003)

    Google Scholar 

  30. Bushnell, M., Agrawal, V.: Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Springer, Berlin/Heidelberg (2000)

    Google Scholar 

  31. Datta, R., Sebastine, A., Raghunathan, A., Abraham, J.: On-chip delay measurement for silicon debug. In: Proceedings of GLSVLSI’ 04, pp. 145–148 (Apr 2004)

    Google Scholar 

  32. Ghosh, S., Bhunia, S., Raychowdhury, A., Roy, K.: A novel delay fault testing methodology using low-overhead built-in delay sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), 2934–2943 (2006)

    Article  Google Scholar 

  33. Ghosh, A., Rao, R., Chuang, C., Brown, R.: On-chip process variation detection and compensation using delay and slew-rate monitoring circuits. In: Proceedings of ISQED’08, pp. 815–820 (Mar 2008)

    Google Scholar 

  34. Su, C., Chen, Y., Huang, M., Chen, G., Lee, C.: All digital built-in delay and crosstalk measurement for on-chip buses. In: Proceedings of DATE’00, pp. 527–531 (Mar 2004)

    Google Scholar 

  35. Wang, X., Tehranipoor, M., Datta, R.: Path-RO: A novel on-chip critical path delay measurement under process variations. In: Proceedings of International Conference on Computer-Aided Design (ICCAD) (Nov 2008)

    Google Scholar 

  36. INOVYS.: Test System for Complex SOCs. http://www.etesters.com/listing/40e8f648-a2d6-23b8-949b-4b3c005c86fb/OcelotZFP

  37. Wang, S., Chen, J., Tehranipoor, M.: Representative critical reliability paths for low-cost and accurate on-chip aging evaluation. In: International Conference on Computer-Aided Design (ICCAD) (2012)

    Google Scholar 

  38. Chen, J., Wang, S., Tehranipoor, M.: Critical-reliability path identification and delay analysis. ACM J. Emerg. Technol. Comput. Syst. (JETC) 10(2) (2014)

    Google Scholar 

  39. Jolliffe, I.T.: Principal Component Analysis, 2nd edn, pp. 150–165. Springer, Berlin/ Heidelberg (2002)

    Google Scholar 

  40. Jin, Y., Makris, Y.: Hardware Trojan detection using path delay fingerprint. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2008)

    Google Scholar 

  41. Xiao, K., Zhang, X., Tehranipoor, M.: A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Des. Test 30(2), 26–34 (2013)

    Article  Google Scholar 

  42. Datta, R., Carpenter, G., Nowka, K., Abraham, J.: A scheme for on-chip timing characterization. In: Proceedings of VTS’06, pp. 24–29 (Apr 2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Kan Xiao .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Xiao, K., Forte, D., (Mark) Tehranipoor, M. (2016). Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits. In: Chang, CH., Potkonjak, M. (eds) Secure System Design and Trustable Computing. Springer, Cham. https://doi.org/10.1007/978-3-319-14971-4_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-14971-4_6

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-14970-7

  • Online ISBN: 978-3-319-14971-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics