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Reducing Implicit Overheads of Soft Error Mitigation Techniques Using Selective Hardening

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FPGAs and Parallel Architectures for Aerospace Applications

Abstract

The use of COTS FPGAs as deployment platform of microprocessor based systems represents an attractive alternative on aerospace applications, because their programmability, performance and cost-effectiveness. However, traditional hardening has a remarkable impact on resources and performance that limits their applicability. Selective hardening, that is protecting only the design’s most error-sensitive parts, reduces significantly overheads keeping a reasonable reliability at the same time. This chapter describes and illustrates, with experimental results, this method and presents a hybrid strategy, called co-hardening, to leverage the benefits of adopting selective hardening on both hardware and software.

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Acknowledgment

This work was funded in part by the Spanish Ministry of Education, Culture and Sports with the project “Developing hybrid fault tolerance techniques for embedded microprocessors” (PHB2012-0158-PC).

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Correspondence to Felipe Restrepo-Calle .

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Restrepo-Calle, F., Cuenca-Asensi, S., Martínez-Álvarez, A. (2016). Reducing Implicit Overheads of Soft Error Mitigation Techniques Using Selective Hardening. In: Kastensmidt, F., Rech, P. (eds) FPGAs and Parallel Architectures for Aerospace Applications. Springer, Cham. https://doi.org/10.1007/978-3-319-14352-1_17

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  • DOI: https://doi.org/10.1007/978-3-319-14352-1_17

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-14351-4

  • Online ISBN: 978-3-319-14352-1

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