Abstract
In recent years, smart devices are transitioning from single core processors to multicore processors to satisfy the growing demands of higher performance and lower power consumption. However, power consumption of multicore processors is increasing, as usage of smart devices become more intense. This situation is one of the most fundamental and important obstacle that the mobile device industries face, to extend the battery life of smart devices. This paper evaluates the power reduction control by the OSCAR Automatic Parallelizing Compiler on an Android platform with the newly developed precise power measurement environment on the ODROID-X2, a development platform with the Samsung Exynos4412 Prime, which consists of 4 ARM Cortex-A9 cores. The OSCAR Compiler enables automatic exploitation of multigrain parallelism within a sequential program, and automatically generates a parallelized code with the OSCAR Multi-Platform API power reduction directives for the purpose of DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating. The paper also introduces a newly developed micro second order pseudo clock gating method to reduce power consumption using WFI (Wait For Interrupt). By inserting GPIO (General Purpose Input Output) control functions into programs, signals appear on the power waveform indicating the point of where the GPIO control was inserted and provides a precise power measurement of the specified program area. The results of the power evaluation for real-time Mpeg2 Decoder show 86.7 % power reduction, namely from 2.79[W] to 0.37[W] and for real-time Optical Flow show 86.5 % power reduction, namely from 2.23[W] to 0.36[W] on 3 core execution.
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References
Taylor, M., Kim, J., Miller, J., Wentzlaff, D.: The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22(2), 25–35 (2002)
Hammond, L., Hubbert, B., Siu, M.: The Stanford Hydra CMP. IEEE Micro 20(2), 71–84 (2000)
Friedrich, J., McCredie, B.: Design of the Power6 microprocessor, pp. 96–97 (2007)
Jeff, B.: Advances in big. LITTLE Technology for power and energy savings, pp. 1–11, (September) (2012)
ARM Corporation: Cortex-A9 Technical Reference Manual http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/DDI0388I_cortex_a9_r4p1_trm.pdf
NVIDIA Corporation: Whitepaper NVIDIA Tegra Multi-processor Architecture, pp. 1–12
Samsung Electronics Co. Ltd.: White Paper of Exynos 5. vol. 1(1) (April 2011) pp. 1–8
Amarasinghe, S., Anderson, J.: An overview of the SUIF compiler for scalable parallel machines, vol. 667 (1995)
Blume, W., Doallo, R., Eigenmann, R.: Parallel programming with polaris. Computer 29(12), 78–82 (1996)
Bondhugula, U., Ramanujam, J., Sadayappan, P.: Pluto: A practical and fully automatic polyhedral parallelizer and locality optimizer. Technical Report OSU-CISRC-10/07-TR70, The Ohio State University (October 2007)
Kasahara, H., Obata, M., Ishizaka, K.: Automatic coarse grain task parallel processing on SMP using openMP. In: Midkiff, S.P., Moreira, J.E., Gupta, M., Chatterjee, S., Ferrante, J., Prins, J.F., Pugh, B., Tseng, C.-W. (eds.) LCPC 2000. LNCS, vol. 2017, pp. 189–207. Springer, Heidelberg (2001)
Obata, M., Shirako, J., Kaminaga, H., Ishizaka, K., Kasahara, H.: Hierarchical parallelism control for multigrain parallel processing. In: Pugh, B., Tseng, C.-W. (eds.) LCPC 2002. LNCS, vol. 2481, pp. 31–44. Springer, Heidelberg (2005)
Kimura, K., Mase, M., Mikami, H., Miyamoto, T., Shirako, J., Kasahara, H.: OSCAR API for real-time low-power multicores and its performance on multicores and SMP servers. In: Gao, G.R., Pollock, L.L., Cavazos, J., Li, X. (eds.) LCPC 2009. LNCS, vol. 5898, pp. 188–202. Springer, Heidelberg (2010)
Shirako, J., Oshiyama, N., Wada, Y., Shikano, H., Kimura, K., Kasahara, H.: Compiler control power saving scheme for multi core processors. In: Ayguadé, E., Baumgartner, G., Ramanujam, J., Sadayappan, P. (eds.) LCPC 2005. LNCS, vol. 4339, pp. 362–376. Springer, Heidelberg (2006)
Hsu, C.H., Kremer, U.: The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation - PLDI ’03, p. 38 (2003)
Chen, G., Malkowski, K., Kandemir, M., Raghavan, P.: Reducing power with performance constraints for parallel sparse applications. http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1420150
Xie, F., Martonosi, M., Malik, S.: Compile-time dynamic voltage scaling settings: Opportunities and limits. In: ACM SIGPLAN Notices (2003)
Martonosi, M., Clark, D., Reddi, V., Connors, D., Brooks, D.: Dynamic-compiler-driven control for microprocessor energy and performance (January 2006). http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1603505
Azevedo, A., Cornea, R., Issenin, I., Gupta, R., Dutt, N., Nicolau, A., Veidenbaum, A.: Architectural and compiler strategies for dynamic power management in the COPPER project. In: Innovative Architecture for Future Generation High-Performance Processors and Systems IWIA-01, pp. 25–34 (2001)
Hardkernel: ODROID-X2. http://www.hardkernel.com/renewal_2011/products/prdt_info.php?g_code=G135235611947
Google: Android Developers. http://developer.android.com/index.html
Linux: CPU hotplug Support in Linux(tm) Kernel. https://www.kernel.org/doc/Documentation/cpu-hotplug.txt
Honda, H., Kasahara, H.: Coarse grain parallelism detection scheme of a fortran program. Syst. Comput. Jpn. 22(12), 24–36 (1991)
Obata, M., Shirako, J., Kaminaga, H.: Hierarchical parallelism control for multigrain parallel processing, pp. 31–44 (2005)
ARM Information Center: GPIO Interfaces. https://www.kernel.org/doc/Documentation/gpio.txt
SAMSUNG ELECTRONICS: Samsung Exynos 4 Quad (Exynos 4412) RISC Microprocessor User’s Manual. (October) (2012)
SAMSUNG ELECTRONICS: Samsung Semiconductors Global Site. https://www.samsung.com/global/business/semiconductor/product/poweric/overview
Lee, C., Potkonjak, M., Mangione-Smith, W.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, pp. 330–335 (1997)
Opencv. http://www.opencv.org
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Yamamoto, H. et al. (2014). OSCAR Compiler Controlled Multicore Power Reduction on Android Platform. In: Cașcaval, C., Montesinos, P. (eds) Languages and Compilers for Parallel Computing. LCPC 2013. Lecture Notes in Computer Science(), vol 8664. Springer, Cham. https://doi.org/10.1007/978-3-319-09967-5_9
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